Publication Type : Conference Paper
Publisher : IEEE
Url : https://doi.org/10.1109/IC2E362166.2024.10827113
Keywords : Data integrity;Memory;Very large scale integration;Neutrons;Fasteners;Error correction codes;Delays;Error correction;Reliability;Hardware design languages;Multiple Cell Upsets (MCUs);Error Correction Code (ECC);Divide-symbol;Xilinx Vivado;Verilog;Cost-effective
Campus : Coimbatore
School : School of Engineering
Year : 2024
Abstract : Memories are prone to error due to neutron induced upsets. Reliable data storage hinges on the detection and correction of these errors. This work explores Multiple Cell Upsets (MCU), induced by a single event that causes adjacent bits in a continuous data stream to get corrupted simultaneously. VLSI technology with its enhanced processing capabilities, conserves seamless data integrity by embedding Error Correction Code (ECC) techniques within the memory. Divide-symbol method is employed to encode the data, and any errors that may have occurred due to MCUs will subsequently be corrected during the decoding process. This simple method is effective, as the reduced mathematical complexity ensures data integrity that is also cost-effective. The implementation of proposed technique in Xilinx Vivado, produces an improvement of 49.2% in area and 35.2% in the timing delays.
Cite this Research Publication : Saravana Kumar R T, Yavanika N, Ramesh S R, Rectifying the Impact of Multiple Cell Upsets in Memory Devices, [source], IEEE, 2024, https://doi.org/10.1109/IC2E362166.2024.10827113