Year : 2025
Secure Image Encryption Using Modified AES with Lorenz Chaotic System-Based S-Box Design
Cite this Research Publication : Maran Ponnambalam, Pulimi Keerthi, Secure Image Encryption Using Modified AES with Lorenz Chaotic System-Based S-Box Design, 2025 IEEE 9th International Conference on Information and Communication Technology (CICT), IEEE, 2025, https://doi.org/10.1109/cict67193.2025.11398925
Publisher : IEEE
Year : 2025
Enhanced Image Security Using Chaotic Sequences and Bit-Level Block Transformations
Cite this Research Publication : P Maran, D Siddartha, K Seshu, Enhanced Image Security Using Chaotic Sequences and Bit-Level Block Transformations, 2025 IEEE 9th International Conference on Information and Communication Technology (CICT), IEEE, 2025, https://doi.org/10.1109/cict67193.2025.11398901
Publisher : IEEE
Year : 2025
Design and Implementation of an IEEE-Compliant Receiver for 2.45 GHz QAM Signals
Cite this Research Publication : Pugalbharani N, Sarveshwaran B, Thivya Selvi AR, P Maran, P Devisowjanya, Design and Implementation of an IEEE-Compliant Receiver for 2.45 GHz QAM Signals, 2025 International Conference on Wireless Communications Signal Processing and Networking (WiSPNET), IEEE, 2025, https://doi.org/10.1109/wispnet64060.2025.11005174
Publisher : IEEE
Year : 2024
Hardware Trojan Design and Analysis in FPGA an Introductory Exploration
Cite this Research Publication : Aghilan A, Maran Ponnambalam, Ganesh Kumar Chellamani, Hardware Trojan Design and Analysis in FPGA an Introductory Exploration, 2024 International Conference on Signal Processing, Computation, Electronics, Power and Telecommunication (IConSCEPT), IEEE, 2024, https://doi.org/10.1109/iconscept61884.2024.10627860
Publisher : IEEE
Year : 2024
An Area-Efficient VLSI Architecture with Ladner-Fischer PPA for High-Speed Pseudo-Random Bit Generation
Cite this Research Publication : S. Saranya, P. Maran, S. D. Bharatula and B. N. K. Reddy, "An Area-Efficient VLSI Architecture with Ladner-Fischer PPA for High-Speed Pseudo-Random Bit Generation," 2024 15th International Conference on Computing Communication and Networking Technologies (ICCCNT), Kamand, India, 2024, pp. 1-5, doi: 10.1109/ICCCNT61001.2024.10725916.
Publisher : IEEE
Year : 2021
Design and Analysis of Sobol Sequence Generator using gray code parallelization
Cite this Research Publication : Akriti Dikshit, Gayathri Prasad, Maran Ponnambalam, Design and Analysis of Sobol Sequence Generator using gray code parallelization, 2021 2nd Global Conference for Advancement in Technology (GCAT), IEEE, 2021, https://doi.org/10.1109/gcat52182.2021.9587580
Publisher : IEEE
Year : 2019
Study and Analysis of the cascoded LNA with and without using inductive degeneration at the common gate for WLAN applications
Cite this Research Publication : K. Shrivastav and P. Maran, "Study and Analysis of the cascoded LNA with and without using inductive degeneration at the common gate for WLAN applications," 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), Kolkata, India, 2019, pp. 1-6.
Publisher : IEEE
Year : 2017
Comparison of tunability and phase noise associated with injection locked three staged single and differential ended VCOs in 90nm CMOS
Cite this Research Publication : Joshapath Johnson, Maran Ponnambalam, Premanand V. Chandramani, "Comparison of tunability and phase noise associated with injection locked three stage single and differential ended VCOs in 90 nm CMOS", ICSCN-2017. 10.1109/ICSCN.2017.8085700
Publisher : IEEE
Year : 2016
Single Event Upset In a 3-Bit SAR ADC
Cite this Research Publication : J Arockia Twinkle, Maran Ponnambalam, Premanand V. Chandramani, "Single Event Upset In a 3-Bit SAR ADC", National Conference on Research Challenges in VLSI Design and Embedded Systems for Wireless Communication, 2016, pp. 31–34.
Publisher : National Conference on Research Challenges in VLSI Design and Embedded Systems for Wireless Communication
Year : 2016
SET induced Soft-error study of two stage ADC with VCO based ADC on the second stage
Cite this Research Publication : Maran Ponnambalam, Premanand V. Chandramani, "SET induced Soft-error study of two stage ADC with VCO based ADC on the second stage", National Conference on Reliability and Safety Engineering, NCRS 2016.
Publisher : National Conference on Reliability and Safety Engineering, NCRS 2016
Year : 2014
Spur reduction technique for fractional-N frequency synthesizer with MASH 1-1-1-1 Sigma Delta modulator
Cite this Research Publication : T. V, P. Maran, and Premanand Venkatesh Chandramani, “Spur reduction technique for fractional-N frequency synthesizer with MASH 1-1-1-1 Sigma Delta modulator”, in 2014 International Conference on Communication and Signal Processing, 2014.
Publisher : 2014 International Conference on Communication and Signal Processing
Year : 2014
Design and implementation of two stage 5-bit pipelined SAR ADC
Cite this Research Publication : A. Padmanaban M., P. Maran, and Premanand Venkatesh Chandramani, “Design and implementation of two stage 5-bit pipelined SAR ADC”, in 2014 International Conference on Communication and Signal Processing, 2014.
Publisher : 2014 International Conference on Communication and Signal Processing
Year : 2013
Injection Locked Differential Ring VCO
Cite this Research Publication : P. Maran, Dr. Premanand Chandramani, "Injection Locked Differential Ring VCO", IEEE International Conference on Information and Communication Technologies (ICT 2013), pp. 1133–1136.
Publisher : 2013 IEEE Conference on Information Communication Technologies
Year : 2012
Design of Control Circuit for Torsion Bar Testing Machine
Cite this Research Publication : P. Maran, Madhankumar, E., and Mathivanan, P., “Design of Control Circuit for Torsion Bar Testing Machine”, in International Conference & Workshop on Recent Trends in Technology, 2012.
Publisher : International Conference Workshop on Recent Trends in Technology