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Dr. Anita J. P.

Associate Professor, Electronics and Communication Engineering, School of Engineering, Coimbatore

Qualification: BE, M.E, Ph.D
jp_anita@cb.amrita.edu
Anita J P's Google Scholar Profile
Research Interest: Very-Large-Scale Integration (VLSI) Design & Testing

Bio

Dr J.P. Anita received her BE in Electronics and Communication Engineering from Government College of Technology, Coimbatore, ME in Applied Electronics from PSG College of Technology, Coimbatore and PhD in the area of VLSI Testing from Anna University. She is presently an Associate Professor in the Department of Electronics and Communication Engineering at Amrita Vishwa Vidyapeetham, Coimbatore. She has published several papers in International Journals and Conferences and also serves as a reviewer for many International Journals. She is a member of many professional bodies. Her research interest includes VLSI Design and Testing, Low Power VLSI and Optimization Algorithms.

Publications

Journal Article

Year : 2023

Improving Robustness of Two Speed Serial Parallel Booth Multiplier Using Fault Detection Mechanism

Cite this Research Publication : Sreelakshmi R, Anita J P, “Improving Robustness of Two Speed Serial Parallel Booth Multiplier Using Fault Detection Mechanism”, Lecture Notes in Electrical Engineering, vol. 977, pp. 1033-1044, 2023

Year : 2023

Generation of Counters and Compressors Using Sorting Network

Cite this Research Publication : Anil Kumar, Anita, J.P , “Generation of Counters and Compressors Using Sorting Network”, Lecture Notes in Electrical Engineering, vol. 977, pp. 35-44, 2023.

Year : 2023

Implementation of Advanced High Performance Bus to Advanced Peripheral Bus Bridge

Cite this Research Publication : Manasa C S, Navya Mohan., Anita, J.P, “Implementation of Advanced High Performance Bus to Advanced Peripheral Bus Bridge”, Lecture Notes in Networks and Systems, vol.563, pp. 179-188, 2023.

Year : 2023

Early Detection of Clustered Trojan Attacks on Integrated Circuits Using Transition Delay Fault Model

Cite this Research Publication : Navya Mohan., Anita, J.P,“ Early Detection of Clustered Trojan Attacks on Integrated Circuits Using Transition Delay Fault Model”, Cryptography, vol. 7, no.1, 2023.

Year : 2022

Design of a High-Speed Binary Counter Using a Stacking Circuit

Cite this Research Publication : Devika C, J P Anita, “Design of a High-Speed Binary Counter Using a Stacking Circuit”, in Lecture Notes in Networks and Systems, Vol. 311, pp. 135-143,2022.

Year : 2022

Design of Multistage Counters Using Linear Feedback Shift Register

Cite this Research Publication : Neethu B Nair, J P Anita , “Design of Multistage Counters Using Linear Feedback Shift Register”, in Lecture Notes in Networks and Systems, Vol. 311, pp. 161-173,2022.

Year : 2022

Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults

Cite this Research Publication : Navya Mohan., Anita, J.P, “Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults” in Integration- the VLSI Journal, vol. 83, pp.24 – 32, 2022.

Year : 2022

Efficient Square Root Computation–An Analysis

Cite this Research Publication : A. Sai Prasanna, J. Tejeswini, P. Keerthana, P. Yamini Raghavi, J. P. Anita “Efficient Square Root Computation–An Analysis”, Lecture Notes in Electrical Engineering, vol. 903, pp. 425-434, 2022.

Year : 2021

Optimization of EOR and ENOR for Design of Full Adders with Efficient Transistor Sizing

Cite this Research Publication : Ghayathri T, Lavanya T, Srivastava Y, Anita J P, “Optimization of EOR and ENOR for Design of Full Adders with Efficient Transistor Sizing” in the International Conference on Trends in Electronics and Informatics, pp 107-112, 2021.

Year : 2021

Property Driven Design based Verification

Cite this Research Publication : Aarthi R, Aishwarya C, Akash M U, Krupasankar P, Yadukrishnan G, Anita J P, “Property Driven Design based Verification”, Proceedings of the International Conference on Communication and Electronics Systems, pp. 1322-1328. 2021

Year : 2020

Structured DFT Based Analysis of Standard Benchmark Circuits

Cite this Research Publication : Shravani H H and J.P.Anita, “Structured DFT based analysis of standard benchmark circuits”, Lecture Notes in Electrical Engineering, vol.569, pp. 705 -715, 2020.

Year : 2020

Identification of faulty locations in digital circuits using SVM classifier

Cite this Research Publication : Hussain, Z., Anita, J.P, “ Identification of faulty locations in digital circuits using SVM classifier”, Proceedings of the International Conference on Trends in Electronics and Informatics, pp. 43-47, 2020.

Year : 2020

Implementation of hybrid LBIST mechanism in digital circuits for test pattern generation and test time reduction

Cite this Research Publication : Kumar, P.A., Anita, J.P, “Implementation of hybrid LBIST mechanism in digital circuits for test pattern generation and test time reduction”, Proceedings of the International Conference on Communication and Electronics Systems, pp. 243-248, 2020.

Year : 2020

Interocular Distance based Facial Recognition

Cite this Research Publication : Sundar, G., Anand, V., and Anita, J.P, “Interocular Distance based Facial Recognition”. Proceedings of International Conference on Communication and Signal Processing, pp. 1478-1481, 2020

Year : 2020

Compact Test and Diagnosis Pattern Generation for Multiple Fault Pairs in Single Run

Cite this Research Publication : Navya Mohan., Anita, J.P, “Compact Test and Diagnosis Pattern Generation for Multiple Fault Pairs in Single Run”, in the Journal of Engineering Science and Technology, vol. 15, No. 6, pp.3820 – 3835, 2020.

Year : 2020

Testing of FPGA Input/output Pins Using BIST

Cite this Research Publication : S Gurusharan, Rahul Adhithya R, S Sri Harish, J P Anita, “Testing of FPGA Input/output Pins Using BIST”, Lecture Notes in Networks and Systems, vol.190, pp. 709 -720, 2020.

Year : 2019

Improving diagnostic test coverage from detection test set for logic circuits

Cite this Research Publication : Madhan B and J.P.Anita, “Improving diagnostic test coverage from detection test set for logic circuits”, Advances in Intelligent Systems and Computing ,Vol.898, pp. 447 -452, 2019.

Year : 2019

Fault diagnosis using automatic test pattern generation and test power reduction technique for VLSI circuits

Cite this Research Publication : Kumar, C.N., Madhumitha, A., Preetam, N.S., Gupta, P.V., Anita, J.P, “Fault diagnosis using automatic test pattern generation and test power reduction technique for VLSI circuits”, Proceedings of the International Conference on Trends in Electronics and Informatics, pp. 412-417, 2019.

Year : 2019

A Diagnosis Pattern Generation Procedure to Distinguish Between Stuck-at and Bridging Faults in Digital Circuits

Cite this Research Publication : Madhumithaa, S.P.M., Aravind, S., Harish, S.P., Ramakrishna Prabhu, C., Anita, J.P, “ A diagnosis pattern generation procedure to distinguish between stuck-at and bridging faults in digital circuits”, Proceedings of the International Conference on Intelligent Computing and Control Systems, pp. 321-325, 2019.

Year : 2019

Online state and parameter estimation of ultra-capacitor using marginalized Kalman filter

Cite this Research Publication : Madhumitha, S., Sudheesh, P., Anita, J.P, “ Online state and parameter estimation of ultra-capacitor using marginalized Kalman filter”, Proceedings of the International Conference on Intelligent Computing and Control Systems, pp. 167-174, 2019

Year : 2019

Test Pattern Generation to Detect Single Stuck-at Faults for Combinational Circuits Using ZBDD

Cite this Research Publication : Thomas, A., Anita, J.P, ” Test Pattern Generation to Detect Single Stuck-at Faults for Combinational Circuits Using ZBDD”, Proceedings of the International Conference on Communication and Electronics Systems, pp. 427-430. 2019

Year : 2019

AXI based DMA Memory System Testbench Architecture Using UVM Harness Technique

Cite this Research Publication : Anjali, Anita, J.P, “ AXI based DMA memory system test bench architecture using UVM harness technique”, Proceedings of the International Conference on Advances in Computing and Communication, pp. 152-157. 2019

Year : 2019

Improving diagnostic test coverage from detection test set for logic circuits

Cite this Research Publication : B. Madhan and Anita, J. P., “Improving diagnostic test coverage from detection test set for logic circuits”, Advances in Intelligent Systems and Computing, vol. 898, pp. 447-452, 2019.

Publisher : Advances in Intelligent Systems and Computing

Year : 2018

Test volume reduction for logic circuits by sharing of test patterns

Cite this Research Publication : K. A. Radhika and Dr. Anita J. P., “Test volume reduction for logic circuits by sharing of test patterns”, International Journal of Pure and Applied Mathematics, vol. 118, pp. 2935-2941, 2018.

Publisher : Academic Press

Year : 2017

Modified carry select adder for power and area reduction

Cite this Research Publication : Abhiram, T., Ashwin, T., Sivaprasad, B., Aakash, S., Anita, J.P “Modified carry select adder for power and area reduction”, Proc. International Conference on Circuit, Power and Computing Technologies, 2017

Year : 2017

Design of a low power, high speed double tail comparator

Cite this Research Publication : Aakash, S., Anisha, A., Das, G.J., Abhiram, T., Anita, J.P, “Design of a low power, high speed double tail comparator”, Proc. International Conference on Circuit, Power and Computing Technologies, 2017.

Year : 2017

Lateral prediction in adaptive cruise control using adaptive particle filter

Cite this Research Publication : Badrinath, J., Anita, J.P., Sudheesh, P, “Lateral prediction in adaptive cruise control using adaptive particle filter”, Proc. International Conference on Advances in Computing, Communications and Informatics, 2017.

Year : 2017

Nonlinear state estimation of wind turbine

Cite this Research Publication : Sudev, P., Anita, J.P., and Sudheesh, P, “Nonlinear state estimation of wind turbine”, Proc. International Conference on Advances in Computing, Communications and Informatics, 2017.

Year : 2017

Tracking of GPS Parameters Using Particle Filter

Cite this Research Publication : M. Nishanth, Anita, J. P., and Sudheesh, P., “Tracking of GPS Parameters Using Particle Filter”, Communications in Computer and Information Science, vol. 746, pp. 411-421, 2017.

Publisher : Communications in Computer and Information Science, Springer Verlag

Year : 2017

Pattern Generation and Test Compression Using PRESTO Generator

Cite this Research Publication : A. Roy and Dr. Anita J. P., “Pattern Generation and Test Compression Using PRESTO Generator”, Communications in Computer and Information Science, vol. 746, pp. 276-285, 2017.

Publisher : Communications in Computer and Information Science, Springer Verlag

Year : 2017

Estimation and Tracking of a Ballistic Target Using Sequential Importance Sampling Method

Cite this Research Publication : J. Ramnarayan, Anita, J. P., and Sudheesh, P., “Estimation and Tracking of a Ballistic Target Using Sequential Importance Sampling Method”, Communications in Computer and Information Science, vol. 746, pp. 387-398, 2017.

Publisher : Springer Verlag

Year : 2016

A compaction based MT filling technique for low power test set generation

Cite this Research Publication : G VenuMadhavi and J. P Anita, “A compaction based MT filling technique for low power test set generation”, Proc. International Conference on Devices, Circuits and Systems, pp. 124-127, 2016

Year : 2016

Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits

Cite this Research Publication : A. Asokan and Dr. Anita J. P., “Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits”, Indian Journal of Science and Technology, vol. 9, no. 30, 2016.

Publisher : Indian Journal of Science and Technology, Indian Society for Education and Environment.

Year : 2016

Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

Cite this Research Publication : Dr. Anita J. P. and Sudheesh, P., “Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams”, International Journal of High Performance Systems Architecture, vol. 6, pp. 51-60, 2016.

Publisher : Inderscience Enterprises Ltd

Year : 2016

A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults

Cite this Research Publication : N. Mohan and Dr. Anita J. P., “A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults”, International Journal of Mathematical Modelling and Numerical Optimisation, vol. 7, pp. 83-96, 2016.

Publisher : Inderscience Enterprises Ltd.

Year : 2015

Static relaxation technique with test vector compression

Cite this Research Publication : Dr. Anita J. P. and Rajan, D., “Static relaxation technique with test vector compression”, International Journal of Applied Engineering Research, vol. 10, no. 11, pp. 28731-28739, 2015.

Publisher : International Journal of Applied Engineering Research

Year : 2012

Multiple fault diagnosis and test power reduction using genetic algorithms

Cite this Research Publication : Dr. Anita J. P. and Vanathi, P. T., “Multiple fault diagnosis and test power reduction using genetic algorithms”, Communications in Computer and Information Science, vol. 305 CCIS, pp. 84-92, 2012.

Publisher : Communications in Computer and Information Science

Conference Paper

Year : 2017

Modified Carry Select Adder for Power and Area Reduction

Cite this Research Publication : T. Abhiram, Ashwin, T., Sivaprasad, B., Aakash, S., and Dr. Anita J. P., “Modified Carry Select Adder for Power and Area Reduction”, in 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT), 2017.

Publisher : ICCPCT

Year : 2017

Design of a Low Power, High Speed Double Tail Comparator

Cite this Research Publication : S. Aakash, Anisha, A., Das, G. J., Abhiram, T., and Dr. Anita J. P., “Design of a Low Power, High Speed Double Tail Comparator”, in 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT), 2017.

Publisher : ICCPCT

Year : 2016

Multistage test data compression technique for VLSI circuits

Cite this Research Publication : A. Asokan and Dr. Anita J. P., “Multistage test data compression technique for VLSI circuits”, in Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016, 2016, pp. 65-68.

Publisher : Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016, Institute of Electrical and Electronics Engineers Inc.

Year : 2016

A Compaction based MT Filling Technique for Low-Power Test Set Generation

Cite this Research Publication : G. V. Madhavi and Dr. Anita J. P., “A Compaction based MT Filling Technique for Low-Power Test Set Generation”, in 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS), 2016, pp. 124-127.

Publisher : 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS), p.124-127.

Year : 2015

Efficient don’t-care filling method to achieve reduction in test power

Cite this Research Publication : V. Sinduja, Raghav, S., and Dr. Anita J. P., “Efficient don't-care filling method to achieve reduction in test power”, in 2015 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2015, 2015, pp. 478-482.

Publisher : Institute of Electrical and Electronics Engineers Inc.,

Year : 2014

Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits

Cite this Research Publication : Dr. Anita J. P. and Vanathi, P. T., “Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits”, in International Conference on Electronics and Communication Systems (ICECS -2014), 2014.

Publisher : International Conference on Electronics and Communication Systems

Year : 2011

Novel approach for multiple arbitrary faults diagnosis in combinational circuits

Cite this Research Publication : R. Raju, Dr. Anita J. P., and Vanathi, P. T., “Novel approach for multiple arbitrary faults diagnosis in combinational circuits”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.

Publisher : Proceedings of 2011 International Conference on Process Automation, Control and Computing

Year : 2010

Multiple fault diagnosis with improved diagnosis resolotion for VLSI circuits

Cite this Research Publication : Dr. Anita J. P. and Vanathi, P. T., “Multiple fault diagnosis with improved diagnosis resolotion for VLSI circuits”, in 2010 2nd International Conference on Computing, Communication and Networking Technologies, ICCCNT 2010, Karur, 2010.

Publisher : ICCCNT 2010

Conference Proceedings

Year : 2017

Particle Filtering Technique for Fast Fading Shadow Power Estimation in Wireless Communication

Cite this Research Publication : J. S. Gopal, Anita, J. P., and Sudheesh, P., “Particle Filtering Technique for Fast Fading Shadow Power Estimation in Wireless Communication”, 3rd international symposium on signal processing and intelligent recognition systems (SIRS17). Springer International Publishing, Cham, pp. 105-115, 2017.

Publisher : Springer International Publishing, Cham

Year : 2016

Diagnosis of Multiple Stuck-at Faults Using Fault Element Graph with Reduced Power

Cite this Research Publication : E. R. Midhila, Swaminathan, A., Lekshmi, B., and Dr. Anita J. P., “Diagnosis of Multiple Stuck-at Faults Using Fault Element Graph with Reduced Power”, Security in Computing and Communications, vol. 625. Springer Singapore, Singapore, pp. 414-426, 2016.

Publisher : Springer Singapore

Qualification
  • 2013: Ph. D. in VLSI Testing
    PSG College of Technology, Coimbatore
  • 2001: M. E. in Applied Electronics
    PSG College of Technology, Coimbatore

Professional Experience
Position Organization Period Domain
Associate Professor Amrita Vishwa Vidyapeetham May, 2023 onwards Teaching, Research and Department Administration.
Assistant Professor- Selection Grade Amrita Vishwa Vidyapeetham July, 2007 Till May, 2023 Teaching, Research and Department Administration.

Academic Responsibilities
S.No Position Class / Batch Responsibility
1. Batch Coordinator 2021-2025 Coordinating the academic and non-academic activities for the batch of 2021-2025 ECE/CCE students
2. PG Project Coordinator 2011-2013 Coordinating the PG Projects and the conduct of project reviews.
3. Department OBE Coordinator 2016-2017 Coordinating the OBE data in terms of CO, PO & PSO attainment.
4 UG Project Coordinator 2013-2014 Coordinating the UG Project activities of the final Year B.Tech students.
5. Class Adviser 2013 -2017
2017-2021
2021-2025.
Mentor the students in their academic and non-academic activities.
6. Academic

Coordinator

2013 – 2017 Coordinating the academically weak students
7. Department Student Counsellor 2020 – 2022 Counselling the students both in academic & non-academic activities.

Undergraduate Courses Handled
  1. Principles of VLSI Testing
  2. Digital Design
  3. Digital IC Design
  4. Network Theory
  5. Circuit Theory
  6. Electronic Circuits
Post-Graduate / Ph. D. Courses Handled
  1. Digital System Design
  2. CMOS Integrated Circuits
  3. Design for Test and Testing
  4. Low Power VLSI Circuits
  5. Design Verification
Organizing Faculty Development / STTP / Workshops /Conferences
SNo Title Organization Period Outcome
1. Honeywell sponsored National Symposium on Green Electronics Amrita University, Coimbatore. December 12 – 13, 2014 Rs 1.5 Lakhs received as sponsorship.
Academic Research – Ph. D. Guidance
S.No Name of the Scholar Specialization / Title Year Status / Year
1. Navya Mohan Unifying the Process of Test and Diagnosis Pattern Generation for Difficult to Distinguish Faults 2016 Graduated
2. Mohankumar N Deterrence of malicious activity in VLSI Circuits by obfuscation 2014 Qualifying Exam
3. Chandra Shaker Arrabotu Effective Offloading of Interdependent Computations in Multi-Access Edge Computing Scenario 2021 Comprehensive Exam
Academic Research – PG Projects

S.No Name of the Scholar Programme Specialization Duration Status
1. Paritala Avinash Kumar VLSI Design Hybrid LBIST 2019-2020 Completed
2. Mohammed Zakir Hussain VLSI Design Faulty locations using SVM Classifier 2019-2020 Completed
3. Devika C VLSI Design FPGA Based Testing 2020-2021 Completed
4. Neethu B Nair VLSI Design Multistage Counters Using Linear Feed-back Shift Register 2020-2021 Completed
5. Chinta Sai Manasa VLSI Design Advanced Peripheral Bus Bridge Implementation 2021-2022 Completed
6. Kolaganti Anil Kuma VLSI Design Testing and Verification 2021-2022 Completed
7. Sreelakshmi R Nair VLSI Design Fault Detection Mechanism 2021-2022 Completed
8. Botcha Sai Mihiraamsh VLSI Design MAC unit using CNN 2022-2023 Completed
9. Pamidi Akanksha VLSI Design ML algorithms for DFT 2022-2023 Completed
10. Sevate Chandra Sekhar VLSI Design Test Compression and Decompression 2022-2023 Completed
11. Guduru Sairama

Chaitanya

VLSI Design Testing and Verification 2023-2024 Ongoing
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