Qualification: 
Ph.D
jp_anita@cb.amrita.edu

Dr. Anita J. P. joined Amrita in June 1996 in the Department of Electronics and Communication Engineering, School of Engineering, Coimbatore campus. She pursued her B. E. in Electronics and Communication Engineering from Government College of Technology, Coimbatore in 1991 and M. E. in Applied Electronics from PSG College of Technology, Coimbatore, in 2001. Her Ph. D. is in the area of VLSI Testing from PSG College of Technology, Coimbatore, in 2013.

She is an Assistant Professor in the Department of Electronics and Communication Engineering at School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore. Her research interest include VLSI Design and Testing, Low Power VLSI and Test Data Compression. She has guided several B. Tech. and M. Tech. projects and has published around 20 papers in international journals and international conferences. She is a reviewer of the Journal of King Saud University - Computer and Information Sciences (Elsevier). She is an active member of ISTE.

Education

  • 2013: Ph. D. in VLSI Testing
    PSG College of Technology - Anna University
  • 2001: M. E. in Applied Electronics
    PSG College of Technology - Bharathiar University
  • 1991: B. E. in Electronics and Communication
    Government College of Technology, Coimbatore

Professional Experience

Year Affiliation
July 1, 2005 to Present Assistant Professor (SG), Amrita Vishwa Vidyapeetham
Domain : VLSI Design and Testing  Low Power VLSI
September 1, 2001 to July 1, 2005 Senior Lecturer, Amrita Vishwa Vidyapeetham
Domain : VLSI Design and Testing  Low Power VLSI
June 3, 1996 to September 1, 2001 Lecturer, Amrita Vishwa Vidyapeetham
Domain : VLSI Design and Testing  Low Power VLSI

Academic Responsibilities

SNo Position Class / Batch
1. Class Adviser ECE A / 2013–2017
ECE D / 2017 – 2021
M.Tech VLSI 2006-2008
2. Batch Coordinator 2013 – 2017
3. UG Project Coordinator 2013 – 2017
3. PG Project Coordinator - VLSI 2011-2013
4. Academic Coordinator 2013-2017
5. Ph. D. Admission Coordinator 2016

Undergraduate Courses Handled

  1. Network Theory
  2. Digital Systems
  3. Digital IC Design
  4. Principles of VLSI Testing
  5. Electronic Circuits
  6. VLSI Design
  7. Electronic Circuits Lab
  8. Digital Systems Lab

Post-Graduate / Ph. D. Courses Handled

  1. VLSI Testing
  2. CMOS Integrated Circuits
  3. Low Power VLSI
  4. Digital Systems

Organizing Faculty Development / STTP / Workshops /Conferences

SNo Title Organization Period Outcome
1. National symposium on Green Electronics. Amrita, Coimbatore December 11 - 13, 2014 Industry experts invited and students benefitted.

Academic Research – Ph. D. Guidance

SNo Name of the Scholar Specialization / Title Duration / Registration Status / Year
1. Navya Mohan VLSI Testing July 2016 (Post-comprehensive)

Academic Research – PG Projects

SNo Name of the Scholar Programme Specialization Duration Status
1. Anju Asokan VLSI Design VLSI Testing and Data Compression 2014-16 Completed
2. G VenuMadhavi VLSI Design VLSI Test Compaction 2014-16 Completed
3 Annu Roy VLSI Design Pattern Generation and Test Compression 2015-17 Completed
4 Radhika K A VLSI Design Test Volume Reduction 2015-17 Completed
5. AmulyaVenkateshappa VLSI Design Logic Encryption 2015-17 Completed
6. Bommidi Madhan VLSI Design Diagnostic Test Coverage 2016-18 Completed
7. Anjali VLSI Design 2017-19 Ongoing
8 Shravani VLSI Design 2017-19 Ongoing

Subjects of Expertise

  • Digital Circuit and Systems
  • VLSI Design
  • Digital IC Design
  • Principles of VLSI Testing
  • Network Theory
  • Circuit Theory

Publications

Publication Type: Journal Article

Year of Publication Title

2018

K. A. Radhika and Dr. Anita J. P., “Test volume reduction for logic circuits by sharing of test patterns”, International Journal of Pure and Applied Mathematics, vol. 118, pp. 2935-2941, 2018.[Abstract]


The proposed paper presents a compact set of test sequence that can be given to a group of logic blocks which are present in the circuit under test (CUT). The different blocks inside a CUT may have different number of primary inputs and the length of the test sequences also varies depending on the design. The compaction of test sequence is performed in such a way that a common set of test sequence can be provided to every blocks inside a design. First the test sequences are expanded based on four expansion techniques. The test sequence is then concatenated and compacted. Test compaction is obtained in the proposed method in which the unnecessary test patterns are removed. The method efficiently reduces the storage required for the test sequence. The generated compact functional test sequences are of reduced size and it only require less amount of storage requirements. The proposed method is applied on ISCAS'89, ISCAS'85 and ITC'99 benchmark circuits and compared in terms of the number of bytes needed for storage of the test sequences. © 2018 Academic Press. All rights reserved.

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2017

A. Roy and Dr. Anita J. P., “Pattern Generation and Test Compression Using PRESTO Generator”, Communications in Computer and Information Science, vol. 746, pp. 276-285, 2017.[Abstract]


The proposed work has a test pattern generator for built-in self-test (BIST) based applications along with test data compression. Test patterns are produced with desired levels of toggling and improved fault coverage is obtained when compared with BIST-based pseudorandom pattern generators (PRPG). The pattern generator comprises of a pseudorandom pattern generation unit, a toggle generation and control unit, a hold register unit. Preselected toggling (PRESTO) generator allows user defined levels of toggling. The pattern generator is a linear finite state machine which drives a phase shifter, which reduces correlation of patterns. This paper proposes a test compression method which elevates the compression efficiency that has not been obtained by conventional compression techniques. It does not need any core logic modifications like test point insertion and thus the compression technique is nonintrusive. This hybrid technique of BIST along with test compression achieves fault coverage above 90%. Experimental results are obtained for ISCAS 85, ISCAS 89 and ITC 99 standard benchmark circuits. The PRESTO generator can effectively function as a decompressor also and hence area is reduced.

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2016

A. Asokan and Dr. Anita J. P., “Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits”, Indian Journal of Science and Technology, vol. 9, no. 30, 2016.[Abstract]


Objectives: VLSI testing plays a very crucial role in the design of a VLSI chip. The advances in technology have led to increasing density of transistors and increased circuit complexity in a chip. With the increasing number of inputs, the memory overheads associated with storing test patterns increases. Thus the test pattern volume needs to be compressed. Methods/Statistical Analysis: In the proposed approach, a hybrid test pattern compression technique is used along with different schemes such as Huffman and Run length encoding. These encoding schemes are applied on ISCAS'85 and ISCAS'89 benchmark circuits and the results are compared and analyzed based on their compression ratio. Findings: In the proposed approach, an improved compression ratio is obtained when compared to the existing techniques in the literature. Application: The memory requirements in Automatic Test Equipment (ATE) to store large test data is reduced.

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2016

Dr. Anita J. P. and Sudheesh, P., “Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams”, International Journal of High Performance Systems Architecture, vol. 6, pp. 51-60, 2016.[Abstract]


An algorithm of test pattern generation for multiple faults is proposed using the zero suppressed decision diagrams (ZBDDs). Test pattern generation plays a major role in the design and testing of any chip. The proposed ZBDD is generated from its corresponding binary decision diagram (BDD). A test ZBDD is obtained from the true and faulty ZBDDs and the test patterns are generated from the test ZBDD. The obtained patterns are reordered because the order in which these patterns are used to test the chip is immaterial as far as the faults are concerned but the transitions between the test patterns affect the test power. Hence, the primary objective of the proposed work is the generation of test patterns for a given set of multiple faults. The next objective is to reduce the test power which is the power consumed during testing. © 2016 Inderscience Enterprises Ltd.

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2016

N. Mohan and Dr. Anita J. P., “A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults”, International Journal of Mathematical Modelling and Numerical Optimisation, vol. 7, pp. 83-96, 2016.[Abstract]


This paper presents a new zero suppressed binary decision diagram (ZBDD)-based approach for obtaining larger number of relaxed bits. These test sets find major application in reducing the power consumed during testing. Experiments performed on single and multiple stuck-at faults using ZBDDs show better results in terms of percentage of relaxation over the existing comparable BDD-based approaches. Moreover using these relaxed test vectors and by suitable X-filling methods average switching activity (ASA) of the circuit can be reduced, which will reduce the power dissipation during testing.

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2015

Dr. Anita J. P. and Rajan, D., “Static relaxation technique with test vector compression”, International Journal of Applied Engineering Research, vol. 10, no. 11, pp. 28731-28739, 2015.

2012

Dr. Anita J. P. and Vanathi, P. T., “Multiple fault diagnosis and test power reduction using genetic algorithms”, Communications in Computer and Information Science, vol. 305 CCIS, pp. 84-92, 2012.[Abstract]


In this paper, a novel method for multiple fault diagnosis is proposed using Genetic Algorithms. Fault diagnosis plays a major role in VLSI Design and Testing. The input test vectors required for testing should be compact and optimized .Genetic Algorithm is a search technique to find approximate solutions to optimization and search problems. The proposed technique uses binary strings as a substitute for chromosomes. The chromosomes (test vectors) are initialized randomly and their fitness value is evaluated. Genetic operations selection, crossover and mutation are performed on this initialized set (initial population) to reproduce better test vectors. The test vectors thus generated are reordered by using a reordering algorithm. The total switching activity among the reordered test vectors is thus optimized and hence the reduction of test power. © 2012 Springer-Verlag.

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Publication Type: Conference Paper

Year of Publication Title

2017

S. Aakash, Anisha, A., Das, G. J., Abhiram, T., and Dr. Anita J. P., “Design of a Low Power, High Speed Double Tail Comparator”, in 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT), 2017.[Abstract]


In the fast moving digital world, it becomes imperative to constantly come up with innovation in digitization. The analog to digital converter is the second most widely used device in the world of electronic circuits. ADCs are composed of dynamic comparators. To overcome the challenges faced due to the digital change, improved versions of the conventional comparator design for high-speed functioning and low power consumption has been proposed. Area is another main factor when keeping in mind the design of these dynamic comparators. 180 nm CMOS technology and a constant supply voltage of 0.8V have been used. A conventional double tail comparator has been designed by adding transistors without hindering the functionality. This provides faster, more efficient modification of the comparator design. A new design for a dynamic regenerative double-tail comparator has been proposed which uses clock-gating techniques. This further reduces the power consumption and provides higher speed by reducing the delay time of the circuit

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2017

T. Abhiram, Ashwin, T., Sivaprasad, B., Aakash, S., and Dr. Anita J. P., “Modified Carry Select Adder for Power and Area Reduction”, in 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT), 2017.[Abstract]


The factors which play a pivotal role in VLSI system design are power, delay and area. In order to carry out fast arithmetic functions in many data processing processors, Carry Select Adders (CSLAs) are widely used because they are one amongst many of the fast adders that could be used for the high speed data processing. CSLAs stand out from the remaining conventional adders in terms of performing faster operations. The scope for reduction in area can be observed from the structure of CSLA. Hence a gate level modification has been proposed for the regular CSLA. Based on this modification 16-b, 32-b, 64-b and 128-b SQRT CSLA has been designed. Parameters such as area, power and delay have been analyzed and compared with the regular SQRT CSLA. The comparison between regular and modified CSLA showed a reduction in area and power. This work proposes the use of simple, optimized and an efficient gate-level modification to significantly reduce the area and power of carry select adder with a slight increase in delay.

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2016

A. Asokan and Dr. Anita J. P., “Multistage test data compression technique for VLSI circuits”, in Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016, 2016, pp. 65-68.[Abstract]


A hybrid test data compression method is presented which is targeted at minimizing the volume of test data, which reduces memory requirements for test data and also time required to test the entire data. The compression scheme is so called hybrid as it combines a transform along with the encoding scheme. In the proposed approach, encoding schemes such as Frequency Directed Run length encoding and Shannon Fano encoding schemes are applied on the transformed data. The proposed scheme is applied on ISCAS'85, ISCAS'89 and ITC'99 benchmark circuits and compared in terms of their compression ratio. © 2016 IEEE.

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2016

G. V. Madhavi and Dr. Anita J. P., “A Compaction based MT Filling Technique for Low-Power Test Set Generation”, in 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS), 2016, pp. 124-127.[Abstract]


VLSI testing plays a major role in verifying the functionality of the design before manufacturing the chip. There is a need to verify the chip at the design level itself so that if the functionality does not match the design specifications, the design can be corrected easily. If the defect is found after manufacturing the chip, it costs ten times more to test the chip at a higher level. This is given by rule of ten. The power dissipation during testing of chip is very high and it has become a challenge for the design and test engineers. The proposed approach addresses this issue by means of generation of test sequences, compacting them, extracting functional test cubes, x-filling the test cubes such that the switching activity minimization is ensured by keeping the fault coverage same. All the algorithms in the proposed approach are implemented using c programming and the same is applied to ISCAS'85 and ISCAS'89 benchmark circuits Switching activity, fault coverage before and after employing proposed approach is determined for the ISCAS benchmark circuits

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2015

V. Sinduja, Raghav, S., and Dr. Anita J. P., “Efficient don't-care filling method to achieve reduction in test power”, in 2015 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2015, 2015, pp. 478-482.[Abstract]


Since VLSI technology has become ubiquitous in today's world, this field is a prime candidate for power reduction. Tremendous growth in chip density and reduction in dimensions contribute to an escalation in clock rate. Delay faults are detected using at-speed scan testing. This paper proposes a novel method to achieve power reduction during scan test by using x-filling. In this paper, ISCAS′89 benchmark circuits have been used with an industrial 90nm technology. The tools used were Synopsys TetraMAX and Synopsys Design Compiler. Experimental results show a considerable reduction in average shift power and average capture power. © 2015 IEEE.

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2014

Dr. Anita J. P. and Vanathi, P. T., “Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits”, in International Conference on Electronics and Communication Systems (ICECS -2014), 2014.[Abstract]


A method of test pattern generation for multiple stuck-at faults in VLSI circuits, using genetic algorithm is proposed. The test patterns were earlier generated for single stuck at faults only but in the proposed work, multiple faults are considered and fault masking is also taken into account when faults are injected. The test patterns to detect the faults are the binary values given as inputs to the circuit under test. These patterns should be compact and also should have minimum switching among them to reduce the test power. Genetic Algorithms (GA) is a search technique to find solutions to optimization and search problems. Hence the proposed work uses GA to generate test patterns. Here the chromosomes in GA are substituted for the test patterns. The test patterns are initialized randomly and their fitness value is evaluated. Now GA operators like selection, crossover and mutation are applied on this initial set to reproduce better test patterns. These generated test patterns are reordered using reordering techniques, don't cares filled by filling techniques to reduce the switching activity among them thus reducing the test power. More »»

2011

R. Raju, Dr. Anita J. P., and Vanathi, P. T., “Novel approach for multiple arbitrary faults diagnosis in combinational circuits”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.[Abstract]


With the advent of VLSI, very complex circuits can be implemented in a single chip. So the need for testing the chip increases with the integration. Fault diagnosis results in improving the circuit design process, the manufacturing yield, cost of testing and also reduces the time to market. Diagnosis of today's complex faults is a challenging problem due to the explosion of the underlying solution space with the increasing number of fault locations. This paper gives a comprehensive framework for logic diagnosis of multiple arbitrary faults that can occur in combinational digital circuits. This approach employs the effect cause analysis for the fault diagnosis. To demonstrate the applicability of the proposed method stuck at faults ,bridging faults, open-interconnect fault, stuck open faults, delay faults and a combination of these faults in the same circuit simultaneously leading to multiple faults are dealt with. © 2011 IEEE. More »»

2010

Dr. Anita J. P. and Vanathi, P. T., “Multiple fault diagnosis with improved diagnosis resolotion for VLSI circuits”, in 2010 2nd International Conference on Computing, Communication and Networking Technologies, ICCCNT 2010, Karur, 2010.[Abstract]


In this paper,a new techniques is proposed for diagnosing multiple faults in a given erroneous circuit with improved diagnosis resolution. The first techniques is based on Single Location At a Time (SLAT) and path tracing techniques which start with an initial fault list obtained from an existing diagnosis method. The single observation - single location at a time (SOSLAT) pattern of a fault will detect that fault at one primary output such that other fault in the list will not mask the fault at that primary output. This can be achieved by deactivating the faults that can be propagated to that particular primary output The second technique follows a Boolean Satisfiability (SAT) based diagnosis. A special kind of test called the Anti-Detecting test (AD) is performed. The AD test restricts the number of test vectors improving the diagnosis time. A SAT based diagnosis is done by converting these test vectors into a set of constraints and solving test using a SAT solver. The solution gives the values of the select lines of the multiplexers (induced as a part of SAT diagnosis) inserted at the fault location of the fault list, indicating the presence or absence of the fault. The above two techniques can be applied together for improved diagnosis resolution and time. ©2010 IEEE.

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Publication Type: Conference Proceedings

Year of Publication Title

2016

E. R. Midhila, Swaminathan, A., Lekshmi, B., and Dr. Anita J. P., “Diagnosis of Multiple Stuck-at Faults Using Fault Element Graph with Reduced Power”, Security in Computing and Communications, vol. 625. Springer Singapore, Singapore, pp. 414-426, 2016.[Abstract]


As the manufacturing processes become more and more advanced as per Moore's law, precise control of silicon process is becoming more and more challenging. This increases the probability of defects and has brought a necessity for testing to ensure fault-free products, making the testing of a chip more complex causing testing challenges.

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