Year : 2019
Improving diagnostic test coverage from detection test set for logic circuits
Cite this Research Publication : B. Madhan and Anita, J. P., “Improving diagnostic test coverage from detection test set for logic circuits”, Advances in Intelligent Systems and Computing, vol. 898, pp. 447-452, 2019.
Publisher : Advances in Intelligent Systems and Computing
Year : 2018
Test volume reduction for logic circuits by sharing of test patterns
Cite this Research Publication : K. A. Radhika and Dr. Anita J. P., “Test volume reduction for logic circuits by sharing of test patterns”, International Journal of Pure and Applied Mathematics, vol. 118, pp. 2935-2941, 2018.
Publisher : Academic Press
Year : 2017
Pattern Generation and Test Compression Using PRESTO Generator
Cite this Research Publication : A. Roy and Dr. Anita J. P., “Pattern Generation and Test Compression Using PRESTO Generator”, Communications in Computer and Information Science, vol. 746, pp. 276-285, 2017.
Publisher : Communications in Computer and Information Science, Springer Verlag
Year : 2016
Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits
Cite this Research Publication : A. Asokan and Dr. Anita J. P., “Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits”, Indian Journal of Science and Technology, vol. 9, no. 30, 2016.
Publisher : Indian Journal of Science and Technology, Indian Society for Education and Environment.
Year : 2016
Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams
Cite this Research Publication : Dr. Anita J. P. and Sudheesh, P., “Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams”, International Journal of High Performance Systems Architecture, vol. 6, pp. 51-60, 2016.
Publisher : Inderscience Enterprises Ltd
Year : 2016
A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults
Cite this Research Publication : N. Mohan and Dr. Anita J. P., “A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults”, International Journal of Mathematical Modelling and Numerical Optimisation, vol. 7, pp. 83-96, 2016.
Publisher : Inderscience Enterprises Ltd.
Year : 2015
Static relaxation technique with test vector compression
Cite this Research Publication : Dr. Anita J. P. and Rajan, D., “Static relaxation technique with test vector compression”, International Journal of Applied Engineering Research, vol. 10, no. 11, pp. 28731-28739, 2015.
Publisher : International Journal of Applied Engineering Research
Year : 2012
Multiple fault diagnosis and test power reduction using genetic algorithms
Cite this Research Publication : Dr. Anita J. P. and Vanathi, P. T., “Multiple fault diagnosis and test power reduction using genetic algorithms”, Communications in Computer and Information Science, vol. 305 CCIS, pp. 84-92, 2012.
Publisher : Communications in Computer and Information Science