Year : 2023
Improving Robustness of Two Speed Serial Parallel Booth Multiplier Using Fault Detection Mechanism
Cite this Research Publication : Sreelakshmi R, Anita J P, “Improving Robustness of Two Speed Serial Parallel Booth Multiplier Using Fault Detection Mechanism”, Lecture Notes in Electrical Engineering, vol. 977, pp. 1033-1044, 2023
Year : 2023
Generation of Counters and Compressors Using Sorting Network
Cite this Research Publication : Anil Kumar, Anita, J.P , “Generation of Counters and Compressors Using Sorting Network”, Lecture Notes in Electrical Engineering, vol. 977, pp. 35-44, 2023.
Year : 2023
Implementation of Advanced High Performance Bus to Advanced Peripheral Bus Bridge
Cite this Research Publication : Manasa C S, Navya Mohan., Anita, J.P, “Implementation of Advanced High Performance Bus to Advanced Peripheral Bus Bridge”, Lecture Notes in Networks and Systems, vol.563, pp. 179-188, 2023.
Year : 2023
Early Detection of Clustered Trojan Attacks on Integrated Circuits Using Transition Delay Fault Model
Cite this Research Publication : Navya Mohan., Anita, J.P,“ Early Detection of Clustered Trojan Attacks on Integrated Circuits Using Transition Delay Fault Model”, Cryptography, vol. 7, no.1, 2023.
Year : 2022
Design of a High-Speed Binary Counter Using a Stacking Circuit
Cite this Research Publication : Devika C, J P Anita, “Design of a High-Speed Binary Counter Using a Stacking Circuit”, in Lecture Notes in Networks and Systems, Vol. 311, pp. 135-143,2022.
Year : 2022
Design of Multistage Counters Using Linear Feedback Shift Register
Cite this Research Publication : Neethu B Nair, J P Anita , “Design of Multistage Counters Using Linear Feedback Shift Register”, in Lecture Notes in Networks and Systems, Vol. 311, pp. 161-173,2022.
Year : 2022
Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults
Cite this Research Publication : Navya Mohan., Anita, J.P, “Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults” in Integration- the VLSI Journal, vol. 83, pp.24 – 32, 2022.
Year : 2022
Efficient Square Root Computation–An Analysis
Cite this Research Publication : A. Sai Prasanna, J. Tejeswini, P. Keerthana, P. Yamini Raghavi, J. P. Anita “Efficient Square Root Computation–An Analysis”, Lecture Notes in Electrical Engineering, vol. 903, pp. 425-434, 2022.
Year : 2021
Optimization of EOR and ENOR for Design of Full Adders with Efficient Transistor Sizing
Cite this Research Publication : Ghayathri T, Lavanya T, Srivastava Y, Anita J P, “Optimization of EOR and ENOR for Design of Full Adders with Efficient Transistor Sizing” in the International Conference on Trends in Electronics and Informatics, pp 107-112, 2021.
Year : 2021
Property Driven Design based Verification
Cite this Research Publication : Aarthi R, Aishwarya C, Akash M U, Krupasankar P, Yadukrishnan G, Anita J P, “Property Driven Design based Verification”, Proceedings of the International Conference on Communication and Electronics Systems, pp. 1322-1328. 2021
Year : 2020
Structured DFT Based Analysis of Standard Benchmark Circuits
Cite this Research Publication : Shravani H H and J.P.Anita, “Structured DFT based analysis of standard benchmark circuits”, Lecture Notes in Electrical Engineering, vol.569, pp. 705 -715, 2020.
Year : 2020
Identification of faulty locations in digital circuits using SVM classifier
Cite this Research Publication : Hussain, Z., Anita, J.P, “ Identification of faulty locations in digital circuits using SVM classifier”, Proceedings of the International Conference on Trends in Electronics and Informatics, pp. 43-47, 2020.
Year : 2020
Implementation of hybrid LBIST mechanism in digital circuits for test pattern generation and test time reduction
Cite this Research Publication : Kumar, P.A., Anita, J.P, “Implementation of hybrid LBIST mechanism in digital circuits for test pattern generation and test time reduction”, Proceedings of the International Conference on Communication and Electronics Systems, pp. 243-248, 2020.
Year : 2020
Interocular Distance based Facial Recognition
Cite this Research Publication : Sundar, G., Anand, V., and Anita, J.P, “Interocular Distance based Facial Recognition”. Proceedings of International Conference on Communication and Signal Processing, pp. 1478-1481, 2020
Year : 2020
Compact Test and Diagnosis Pattern Generation for Multiple Fault Pairs in Single Run
Cite this Research Publication : Navya Mohan., Anita, J.P, “Compact Test and Diagnosis Pattern Generation for Multiple Fault Pairs in Single Run”, in the Journal of Engineering Science and Technology, vol. 15, No. 6, pp.3820 – 3835, 2020.
Year : 2020
Testing of FPGA Input/output Pins Using BIST
Cite this Research Publication : S Gurusharan, Rahul Adhithya R, S Sri Harish, J P Anita, “Testing of FPGA Input/output Pins Using BIST”, Lecture Notes in Networks and Systems, vol.190, pp. 709 -720, 2020.
Year : 2019
Improving diagnostic test coverage from detection test set for logic circuits
Cite this Research Publication : Madhan B and J.P.Anita, “Improving diagnostic test coverage from detection test set for logic circuits”, Advances in Intelligent Systems and Computing ,Vol.898, pp. 447 -452, 2019.
Year : 2019
Fault diagnosis using automatic test pattern generation and test power reduction technique for VLSI circuits
Cite this Research Publication : Kumar, C.N., Madhumitha, A., Preetam, N.S., Gupta, P.V., Anita, J.P, “Fault diagnosis using automatic test pattern generation and test power reduction technique for VLSI circuits”, Proceedings of the International Conference on Trends in Electronics and Informatics, pp. 412-417, 2019.
Year : 2019
A Diagnosis Pattern Generation Procedure to Distinguish Between Stuck-at and Bridging Faults in Digital Circuits
Cite this Research Publication : Madhumithaa, S.P.M., Aravind, S., Harish, S.P., Ramakrishna Prabhu, C., Anita, J.P, “ A diagnosis pattern generation procedure to distinguish between stuck-at and bridging faults in digital circuits”, Proceedings of the International Conference on Intelligent Computing and Control Systems, pp. 321-325, 2019.
Year : 2019
Online state and parameter estimation of ultra-capacitor using marginalized Kalman filter
Cite this Research Publication : Madhumitha, S., Sudheesh, P., Anita, J.P, “ Online state and parameter estimation of ultra-capacitor using marginalized Kalman filter”, Proceedings of the International Conference on Intelligent Computing and Control Systems, pp. 167-174, 2019
Year : 2019
Test Pattern Generation to Detect Single Stuck-at Faults for Combinational Circuits Using ZBDD
Cite this Research Publication : Thomas, A., Anita, J.P, ” Test Pattern Generation to Detect Single Stuck-at Faults for Combinational Circuits Using ZBDD”, Proceedings of the International Conference on Communication and Electronics Systems, pp. 427-430. 2019
Year : 2019
AXI based DMA Memory System Testbench Architecture Using UVM Harness Technique
Cite this Research Publication : Anjali, Anita, J.P, “ AXI based DMA memory system test bench architecture using UVM harness technique”, Proceedings of the International Conference on Advances in Computing and Communication, pp. 152-157. 2019
Year : 2019
Improving diagnostic test coverage from detection test set for logic circuits
Cite this Research Publication : B. Madhan and Anita, J. P., “Improving diagnostic test coverage from detection test set for logic circuits”, Advances in Intelligent Systems and Computing, vol. 898, pp. 447-452, 2019.
Publisher : Advances in Intelligent Systems and Computing
Year : 2018
Test volume reduction for logic circuits by sharing of test patterns
Cite this Research Publication : K. A. Radhika and Dr. Anita J. P., “Test volume reduction for logic circuits by sharing of test patterns”, International Journal of Pure and Applied Mathematics, vol. 118, pp. 2935-2941, 2018.
Publisher : Academic Press
Year : 2017
Modified carry select adder for power and area reduction
Cite this Research Publication : Abhiram, T., Ashwin, T., Sivaprasad, B., Aakash, S., Anita, J.P “Modified carry select adder for power and area reduction”, Proc. International Conference on Circuit, Power and Computing Technologies, 2017
Year : 2017
Design of a low power, high speed double tail comparator
Cite this Research Publication : Aakash, S., Anisha, A., Das, G.J., Abhiram, T., Anita, J.P, “Design of a low power, high speed double tail comparator”, Proc. International Conference on Circuit, Power and Computing Technologies, 2017.
Year : 2017
Lateral prediction in adaptive cruise control using adaptive particle filter
Cite this Research Publication : Badrinath, J., Anita, J.P., Sudheesh, P, “Lateral prediction in adaptive cruise control using adaptive particle filter”, Proc. International Conference on Advances in Computing, Communications and Informatics, 2017.
Year : 2017
Nonlinear state estimation of wind turbine
Cite this Research Publication : Sudev, P., Anita, J.P., and Sudheesh, P, “Nonlinear state estimation of wind turbine”, Proc. International Conference on Advances in Computing, Communications and Informatics, 2017.
Year : 2017
Tracking of GPS Parameters Using Particle Filter
Cite this Research Publication : M. Nishanth, Anita, J. P., and Sudheesh, P., “Tracking of GPS Parameters Using Particle Filter”, Communications in Computer and Information Science, vol. 746, pp. 411-421, 2017.
Publisher : Communications in Computer and Information Science, Springer Verlag
Year : 2017
Pattern Generation and Test Compression Using PRESTO Generator
Cite this Research Publication : A. Roy and Dr. Anita J. P., “Pattern Generation and Test Compression Using PRESTO Generator”, Communications in Computer and Information Science, vol. 746, pp. 276-285, 2017.
Publisher : Communications in Computer and Information Science, Springer Verlag
Year : 2017
Estimation and Tracking of a Ballistic Target Using Sequential Importance Sampling Method
Cite this Research Publication : J. Ramnarayan, Anita, J. P., and Sudheesh, P., “Estimation and Tracking of a Ballistic Target Using Sequential Importance Sampling Method”, Communications in Computer and Information Science, vol. 746, pp. 387-398, 2017.
Publisher : Springer Verlag
Year : 2016
A Zero Suppressed Binary Decision Diagram based test set relaxation for single and multiple stuck-at faults
Cite this Research Publication : Navya Mohan, J.P. Anita, “A Zero Suppressed Binary Decision Diagram based test set relaxation for single and multiple stuck-at faults” in the International Journal of Mathematical Modelling and Numerical Optimization, Vol. 7, No.1, pp 83-96, 2016
Year : 2016
A compaction based MT filling technique for low power test set generation
Cite this Research Publication : G VenuMadhavi and J. P Anita, “A compaction based MT filling technique for low power test set generation”, Proc. International Conference on Devices, Circuits and Systems, pp. 124-127, 2016
Year : 2016
A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults
Cite this Research Publication : N. Mohan and Dr. Anita J. P., “A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults”, International Journal of Mathematical Modelling and Numerical Optimisation, vol. 7, pp. 83-96, 2016.
Publisher : Inderscience Enterprises Ltd.
Year : 2016
Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams
Cite this Research Publication : Dr. Anita J. P. and Sudheesh, P., “Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams”, International Journal of High Performance Systems Architecture, vol. 6, pp. 51-60, 2016.
Publisher : Inderscience Enterprises Ltd
Year : 2016
Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits
Cite this Research Publication : A. Asokan and Dr. Anita J. P., “Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits”, Indian Journal of Science and Technology, vol. 9, no. 30, 2016.
Publisher : Indian Journal of Science and Technology, Indian Society for Education and Environment.
Year : 2015
Static relaxation technique with test vector compression
Cite this Research Publication : Dr. Anita J. P. and Rajan, D., “Static relaxation technique with test vector compression”, International Journal of Applied Engineering Research, vol. 10, no. 11, pp. 28731-28739, 2015.
Publisher : International Journal of Applied Engineering Research
Year : 2012
Multiple fault diagnosis and test power reduction using genetic algorithms
Cite this Research Publication : Dr. Anita J. P. and Vanathi, P. T., “Multiple fault diagnosis and test power reduction using genetic algorithms”, Communications in Computer and Information Science, vol. 305 CCIS, pp. 84-92, 2012.
Publisher : Communications in Computer and Information Science