Dr. Anita J. P. joined Amrita in June 1996 in the Department of Electronics and Communication Engineering. She pursued her BE in Electronics and Communication Engineering from Government College of Technology, Coimbatore in 1991 and ME in Applied Electronics from PSG College of Technology, Coimbatore in 2001 and her PhD in the area of VLSI Testing from Anna University in 2013.

She is an Assistant Professor in the Department of Electronics and Communication Engineering at Amrita School of Engineering, Coimbatore. Her research interest include VLSI Design and Testing, Low Power VLSI and Test Data Compression. She has guided several B.Tech. and M.Tech. projects and has published around 20 papers in international journals and international conferences. She is a reviewer of the Journal of King Saud University - Computer and Information Sciences (Elsevier). She is an active member of ISTE.

Research Expertise

  • Guiding a PhD scholar in the area of VLSI design, testing and test data compression.

UG / PG Student Projects

  • Test power reduction and test pattern generation using PSO
  • Test power reduction and test pattern generation using ZBDDs
  • Multiple fault diagnosis of digital circuits using the optimal neural network model
  • Multiple fault diagnosis in VLSI circuits using Binary decision diagrams
  • Failure diagnosis of combinational logic circuits
  • Static relaxation technique with test vector compression
  • Diagnostic fault simulation and test generation using Z-diagnosis
  • Test set relaxation using Binary Decision Diagrams
  • Reduction of test power using don’t-care filling of transition fault test vectors
  • Multiple fault diagnosis using boolean satisfiability
  • Multiple fault diagnosis using single observation single location at a time
  • Dynamic power minimization in combinational circuits
  • Test pattern generation for combinational circuits using sub circuits based method
  • An ATPG for sequential circuits based on genetic algorithms

Subjects of Expertise

  • Digital Circuit and Systems
  • VLSI Design
  • Digital IC Design
  • Principles of VLSI Testing
  • Network Theory
  • Circuit Theory


Publication Type: Journal Article

Year of Publication Title


K. A. Radhika and Dr. Anita J. P., “Test volume reduction for logic circuits by sharing of test patterns”, International Journal of Pure and Applied Mathematics, vol. 118, pp. 2935-2941, 2018.[Abstract]

The proposed paper presents a compact set of test sequence that can be given to a group of logic blocks which are present in the circuit under test (CUT). The different blocks inside a CUT may have different number of primary inputs and the length of the test sequences also varies depending on the design. The compaction of test sequence is performed in such a way that a common set of test sequence can be provided to every blocks inside a design. First the test sequences are expanded based on four expansion techniques. The test sequence is then concatenated and compacted. Test compaction is obtained in the proposed method in which the unnecessary test patterns are removed. The method efficiently reduces the storage required for the test sequence. The generated compact functional test sequences are of reduced size and it only require less amount of storage requirements. The proposed method is applied on ISCAS'89, ISCAS'85 and ITC'99 benchmark circuits and compared in terms of the number of bytes needed for storage of the test sequences. © 2018 Academic Press. All rights reserved.

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Dr. Anita J. P. and Sudheesh, P., “Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams”, International Journal of High Performance Systems Architecture, vol. 6, pp. 51-60, 2016.[Abstract]

An algorithm of test pattern generation for multiple faults is proposed using the zero suppressed decision diagrams (ZBDDs). Test pattern generation plays a major role in the design and testing of any chip. The proposed ZBDD is generated from its corresponding binary decision diagram (BDD). A test ZBDD is obtained from the true and faulty ZBDDs and the test patterns are generated from the test ZBDD. The obtained patterns are reordered because the order in which these patterns are used to test the chip is immaterial as far as the faults are concerned but the transitions between the test patterns affect the test power. Hence, the primary objective of the proposed work is the generation of test patterns for a given set of multiple faults. The next objective is to reduce the test power which is the power consumed during testing. © 2016 Inderscience Enterprises Ltd.

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N. Mohan and Dr. Anita J. P., “A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults”, International Journal of Mathematical Modelling and Numerical Optimisation, vol. 7, pp. 83-96, 2016.[Abstract]

This paper presents a new zero suppressed binary decision diagram (ZBDD)-based approach for obtaining larger number of relaxed bits. These test sets find major application in reducing the power consumed during testing. Experiments performed on single and multiple stuck-at faults using ZBDDs show better results in terms of percentage of relaxation over the existing comparable BDD-based approaches. Moreover using these relaxed test vectors and by suitable X-filling methods average switching activity (ASA) of the circuit can be reduced, which will reduce the power dissipation during testing. © Copyright 2016 Inderscience Enterprises Ltd.

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Dr. Anita J. P. and Rajan, D., “Static relaxation technique with test vector compression”, International Journal of Applied Engineering Research, vol. 10, no. 11, pp. 28731-28739, 2015.


Dr. Anita J. P. and Vanathi, P. T., “Multiple fault diagnosis and test power reduction using genetic algorithms”, Communications in Computer and Information Science, vol. 305 CCIS, pp. 84-92, 2012.[Abstract]

In this paper, a novel method for multiple fault diagnosis is proposed using Genetic Algorithms. Fault diagnosis plays a major role in VLSI Design and Testing. The input test vectors required for testing should be compact and optimized .Genetic Algorithm is a search technique to find approximate solutions to optimization and search problems. The proposed technique uses binary strings as a substitute for chromosomes. The chromosomes (test vectors) are initialized randomly and their fitness value is evaluated. Genetic operations selection, crossover and mutation are performed on this initialized set (initial population) to reproduce better test vectors. The test vectors thus generated are reordered by using a reordering algorithm. The total switching activity among the reordered test vectors is thus optimized and hence the reduction of test power. © 2012 Springer-Verlag.

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Publication Type: Conference Paper

Year of Publication Title


A. Asokan and Dr. Anita J. P., “Multistage test data compression technique for VLSI circuits”, in Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016, 2016, pp. 65-68.[Abstract]

A hybrid test data compression method is presented which is targeted at minimizing the volume of test data, which reduces memory requirements for test data and also time required to test the entire data. The compression scheme is so called hybrid as it combines a transform along with the encoding scheme. In the proposed approach, encoding schemes such as Frequency Directed Run length encoding and Shannon Fano encoding schemes are applied on the transformed data. The proposed scheme is applied on ISCAS'85, ISCAS'89 and ITC'99 benchmark circuits and compared in terms of their compression ratio. © 2016 IEEE.

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V. Sinduja, Raghav, S., and Dr. Anita J. P., “Efficient don't-care filling method to achieve reduction in test power”, in 2015 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2015, 2015, pp. 478-482.[Abstract]

Since VLSI technology has become ubiquitous in today's world, this field is a prime candidate for power reduction. Tremendous growth in chip density and reduction in dimensions contribute to an escalation in clock rate. Delay faults are detected using at-speed scan testing. This paper proposes a novel method to achieve power reduction during scan test by using x-filling. In this paper, ISCAS′89 benchmark circuits have been used with an industrial 90nm technology. The tools used were Synopsys TetraMAX and Synopsys Design Compiler. Experimental results show a considerable reduction in average shift power and average capture power. © 2015 IEEE.

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Dr. Anita J. P. and Vanathi, P. T., “Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits”, in International Conference on Electronics and Communication Systems (ICECS -2014), 2014.[Abstract]

A method of test pattern generation for multiple stuck-at faults in VLSI circuits, using genetic algorithm is proposed. The test patterns were earlier generated for single stuck at faults only but in the proposed work, multiple faults are considered and fault masking is also taken into account when faults are injected. The test patterns to detect the faults are the binary values given as inputs to the circuit under test. These patterns should be compact and also should have minimum switching among them to reduce the test power. Genetic Algorithms (GA) is a search technique to find solutions to optimization and search problems. Hence the proposed work uses GA to generate test patterns. Here the chromosomes in GA are substituted for the test patterns. The test patterns are initialized randomly and their fitness value is evaluated. Now GA operators like selection, crossover and mutation are applied on this initial set to reproduce better test patterns. These generated test patterns are reordered using reordering techniques, don't cares filled by filling techniques to reduce the switching activity among them thus reducing the test power. More »»


R. Raju, Dr. Anita J. P., and Vanathi, P. T., “Novel approach for multiple arbitrary faults diagnosis in combinational circuits”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.[Abstract]

With the advent of VLSI, very complex circuits can be implemented in a single chip. So the need for testing the chip increases with the integration. Fault diagnosis results in improving the circuit design process, the manufacturing yield, cost of testing and also reduces the time to market. Diagnosis of today's complex faults is a challenging problem due to the explosion of the underlying solution space with the increasing number of fault locations. This paper gives a comprehensive framework for logic diagnosis of multiple arbitrary faults that can occur in combinational digital circuits. This approach employs the effect cause analysis for the fault diagnosis. To demonstrate the applicability of the proposed method stuck at faults ,bridging faults, open-interconnect fault, stuck open faults, delay faults and a combination of these faults in the same circuit simultaneously leading to multiple faults are dealt with. © 2011 IEEE. More »»


Dr. Anita J. P. and Vanathi, P. T., “Multiple fault diagnosis with improved diagnosis resolotion for VLSI circuits”, in 2010 2nd International Conference on Computing, Communication and Networking Technologies, ICCCNT 2010, Karur, 2010.[Abstract]

In this paper,a new techniques is proposed for diagnosing multiple faults in a given erroneous circuit with improved diagnosis resolution. The first techniques is based on Single Location At a Time (SLAT) and path tracing techniques which start with an initial fault list obtained from an existing diagnosis method. The single observation - single location at a time (SOSLAT) pattern of a fault will detect that fault at one primary output such that other fault in the list will not mask the fault at that primary output. This can be achieved by deactivating the faults that can be propagated to that particular primary output The second technique follows a Boolean Satisfiability (SAT) based diagnosis. A special kind of test called the Anti-Detecting test (AD) is performed. The AD test restricts the number of test vectors improving the diagnosis time. A SAT based diagnosis is done by converting these test vectors into a set of constraints and solving test using a SAT solver. The solution gives the values of the select lines of the multiplexers (induced as a part of SAT diagnosis) inserted at the fault location of the fault list, indicating the presence or absence of the fault. The above two techniques can be applied together for improved diagnosis resolution and time. ©2010 IEEE.

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