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Dr. Anita J. P.

Assistant Professor (S.G), Electronics and Communication Engineering, School of Engineering, Coimbatore

Qualification: BE, M.E, Ph.D
jp_anita@cb.amrita.edu
Anita J P's Google Scholar Profile
Research Interest: Low Power VLSI, Test Data Compression, Very-Large-Scale Integration (VLSI) Design & Testing

Bio Publications Education Professional Experience Academic Responsibilities Undergraduate Courses Handled Post-Graduate / Ph. D. Courses Handled Organizing Faculty Development / STTP / Workshops /Conferences Academic Research – Ph. D. Guidance Academic Research – PG Projects Subjects of Expertise
Bio

Dr. Anita J. P. joined Amrita in June 1996 in the Department of Electronics and Communication Engineering, School of Engineering, Coimbatore campus. She pursued her B. E. in Electronics and Communication Engineering from Government College of Technology, Coimbatore in 1991 and M. E. in Applied Electronics from PSG College of Technology, Coimbatore, in 2001. Her Ph. D. is in the area of VLSI Testing from PSG College of Technology, Coimbatore, in 2013.

She is an Assistant Professor (S. G) in the Department of Electronics and Communication Engineering at School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore. Her research interest include VLSI Design and Testing, Low Power VLSI and Test Data Compression. She has guided several B. Tech. and M. Tech. projects and has published around 20 papers in international journals and international conferences. She is a reviewer of the Journal of King Saud University – Computer and Information Sciences (Elsevier). She is an active member of ISTE.

 

Publications

Journal Article

Year : 2019

Improving diagnostic test coverage from detection test set for logic circuits

Cite this Research Publication : B. Madhan and Anita, J. P., “Improving diagnostic test coverage from detection test set for logic circuits”, Advances in Intelligent Systems and Computing, vol. 898, pp. 447-452, 2019.

Publisher : Advances in Intelligent Systems and Computing

Year : 2018

Test volume reduction for logic circuits by sharing of test patterns

Cite this Research Publication : K. A. Radhika and Dr. Anita J. P., “Test volume reduction for logic circuits by sharing of test patterns”, International Journal of Pure and Applied Mathematics, vol. 118, pp. 2935-2941, 2018.

Publisher : Academic Press

Year : 2017

Pattern Generation and Test Compression Using PRESTO Generator

Cite this Research Publication : A. Roy and Dr. Anita J. P., “Pattern Generation and Test Compression Using PRESTO Generator”, Communications in Computer and Information Science, vol. 746, pp. 276-285, 2017.

Publisher : Communications in Computer and Information Science, Springer Verlag

Year : 2016

Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits

Cite this Research Publication : A. Asokan and Dr. Anita J. P., “Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits”, Indian Journal of Science and Technology, vol. 9, no. 30, 2016.

Publisher : Indian Journal of Science and Technology, Indian Society for Education and Environment.

Year : 2016

Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

Cite this Research Publication : Dr. Anita J. P. and Sudheesh, P., “Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams”, International Journal of High Performance Systems Architecture, vol. 6, pp. 51-60, 2016.

Publisher : Inderscience Enterprises Ltd

Year : 2016

A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults

Cite this Research Publication : N. Mohan and Dr. Anita J. P., “A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults”, International Journal of Mathematical Modelling and Numerical Optimisation, vol. 7, pp. 83-96, 2016.

Publisher : Inderscience Enterprises Ltd.

Year : 2015

Static relaxation technique with test vector compression

Cite this Research Publication : Dr. Anita J. P. and Rajan, D., “Static relaxation technique with test vector compression”, International Journal of Applied Engineering Research, vol. 10, no. 11, pp. 28731-28739, 2015.

Publisher : International Journal of Applied Engineering Research

Year : 2012

Multiple fault diagnosis and test power reduction using genetic algorithms

Cite this Research Publication : Dr. Anita J. P. and Vanathi, P. T., “Multiple fault diagnosis and test power reduction using genetic algorithms”, Communications in Computer and Information Science, vol. 305 CCIS, pp. 84-92, 2012.

Publisher : Communications in Computer and Information Science

Conference Paper

Year : 2017

Modified Carry Select Adder for Power and Area Reduction

Cite this Research Publication : T. Abhiram, Ashwin, T., Sivaprasad, B., Aakash, S., and Dr. Anita J. P., “Modified Carry Select Adder for Power and Area Reduction”, in 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT), 2017.

Publisher : ICCPCT

Year : 2017

Design of a Low Power, High Speed Double Tail Comparator

Cite this Research Publication : S. Aakash, Anisha, A., Das, G. J., Abhiram, T., and Dr. Anita J. P., “Design of a Low Power, High Speed Double Tail Comparator”, in 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT), 2017.

Publisher : ICCPCT

Year : 2016

Multistage test data compression technique for VLSI circuits

Cite this Research Publication : A. Asokan and Dr. Anita J. P., “Multistage test data compression technique for VLSI circuits”, in Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016, 2016, pp. 65-68.

Publisher : Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016, Institute of Electrical and Electronics Engineers Inc.

Year : 2016

A Compaction based MT Filling Technique for Low-Power Test Set Generation

Cite this Research Publication : G. V. Madhavi and Dr. Anita J. P., “A Compaction based MT Filling Technique for Low-Power Test Set Generation”, in 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS), 2016, pp. 124-127.

Publisher : 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS), p.124-127.

Year : 2015

Efficient don’t-care filling method to achieve reduction in test power

Cite this Research Publication : V. Sinduja, Raghav, S., and Dr. Anita J. P., “Efficient don't-care filling method to achieve reduction in test power”, in 2015 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2015, 2015, pp. 478-482.

Publisher : Institute of Electrical and Electronics Engineers Inc.,

Year : 2014

Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits

Cite this Research Publication : Dr. Anita J. P. and Vanathi, P. T., “Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits”, in International Conference on Electronics and Communication Systems (ICECS -2014), 2014.

Publisher : International Conference on Electronics and Communication Systems

Year : 2011

Novel approach for multiple arbitrary faults diagnosis in combinational circuits

Cite this Research Publication : R. Raju, Dr. Anita J. P., and Vanathi, P. T., “Novel approach for multiple arbitrary faults diagnosis in combinational circuits”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.

Publisher : Proceedings of 2011 International Conference on Process Automation, Control and Computing

Year : 2010

Multiple fault diagnosis with improved diagnosis resolotion for VLSI circuits

Cite this Research Publication : Dr. Anita J. P. and Vanathi, P. T., “Multiple fault diagnosis with improved diagnosis resolotion for VLSI circuits”, in 2010 2nd International Conference on Computing, Communication and Networking Technologies, ICCCNT 2010, Karur, 2010.

Publisher : ICCCNT 2010

Conference Proceedings

Year : 2016

Diagnosis of Multiple Stuck-at Faults Using Fault Element Graph with Reduced Power

Cite this Research Publication : E. R. Midhila, Swaminathan, A., Lekshmi, B., and Dr. Anita J. P., “Diagnosis of Multiple Stuck-at Faults Using Fault Element Graph with Reduced Power”, Security in Computing and Communications, vol. 625. Springer Singapore, Singapore, pp. 414-426, 2016.

Publisher : Springer Singapore

Education
  • 2013: Ph. D. in VLSI Testing
    PSG College of Technology – Anna University
  • 2001: M. E. in Applied Electronics
    PSG College of Technology – Bharathiar University
  • 1991: B. E. in Electronics and Communication
    Government College of Technology, Coimbatore
Professional Experience
Year Affiliation
July 1, 2005 to Present Assistant Professor (SG), Amrita Vishwa Vidyapeetham
Domain : VLSI Design and Testing  Low Power VLSI
September 1, 2001 to July 1, 2005 Senior Lecturer, Amrita Vishwa Vidyapeetham
Domain : VLSI Design and Testing  Low Power VLSI
June 3, 1996 to September 1, 2001 Lecturer, Amrita Vishwa Vidyapeetham
Domain : VLSI Design and Testing  Low Power VLSI
Academic Responsibilities
SNo Position Class / Batch
1. Class Adviser ECE A / 2013–2017
ECE D / 2017 – 2021
M.Tech VLSI 2006-2008
2. Batch Coordinator 2013 – 2017
3. UG Project Coordinator 2013 – 2017
3. PG Project Coordinator – VLSI 2011-2013
4. Academic Coordinator 2013-2017
5. Ph. D. Admission Coordinator 2016
Undergraduate Courses Handled
  1. Network Theory
  2. Digital Systems
  3. Digital IC Design
  4. Principles of VLSI Testing
  5. Electronic Circuits
  6. VLSI Design
  7. Electronic Circuits Lab
  8. Digital Systems Lab
Post-Graduate / Ph. D. Courses Handled
  1. VLSI Testing
  2. CMOS Integrated Circuits
  3. Low Power VLSI
  4. Digital Systems
Organizing Faculty Development / STTP / Workshops /Conferences
SNo Title Organization Period Outcome
1. National symposium on Green Electronics. Amrita, Coimbatore December 11 – 13, 2014 Industry experts invited and students benefitted.
Academic Research – Ph. D. Guidance
SNo Name of the Scholar Specialization / Title Duration / Registration Status / Year
1. Navya Mohan VLSI Testing July 2016 (Post-comprehensive)
Academic Research – PG Projects
SNo Name of the Scholar Programme Specialization Duration Status
1. Anju Asokan VLSI Design VLSI Testing and Data Compression 2014-16 Completed
2. G VenuMadhavi VLSI Design VLSI Test Compaction 2014-16 Completed
3 Annu Roy VLSI Design Pattern Generation and Test Compression 2015-17 Completed
4 Radhika K A VLSI Design Test Volume Reduction 2015-17 Completed
5. AmulyaVenkateshappa VLSI Design Logic Encryption 2015-17 Completed
6. Bommidi Madhan VLSI Design Diagnostic Test Coverage 2016-18 Completed
7. Anjali VLSI Design 2017-19 Ongoing
8 Shravani VLSI Design 2017-19 Ongoing
Subjects of Expertise
  • Digital Circuit and Systems
  • VLSI Design
  • Digital IC Design
  • Principles of VLSI Testing
  • Network Theory
  • Circuit Theory
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