Qualification:
Ph.D
pritambhattacharjee@am.amrita.edu

Dr. Pritam Bhattacharjee currently serves as an Assistant Professor (Senior Grade) at the Department of Computer Science and Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Amritapuri. He received his B.Tech. (in Electronics & Communication Engineering) and M. Tech. (in Microelectronics & VLSI) from Maulana Abul Kalam Azad University of Technology, West Bengal, in the year 2011 and 2013 respectively. His higher education includes full-time Ph.D. (Engg.) research supported by Visvesvaraya Ph.D. Scheme, Government of India at National Institute of Technology, Arunachal Pradesh, which got completed in the year 2020. He has also spent 1 year with Intel Technology India Pvt. Ltd., Bangalore, as the Graduate Intern Technical in Graphics Throughput & Computing Hardware Engineering (GTCHE) team.

Dr. Pritam is currently involved in various teaching/research-related areas like problems of power management in digital/analog integrated-circuits (ICs); quantum-dot cellular automata (QCA) based circuit design; applications of quantum computing and artificial intelligence in different domains.

Publications

Publication Type: Conference Paper

Year of Publication Title

2020

Dr. Pritam Bhattacharjee, “A QCA Based Improvised TRNG Design for the Implementation of Secured Nano Communication Protocol in ATM Services”, in 3rd International Conference on Computational Advancement in Communication Circuit and System (ICCACCS 2020), 2020.

2020

Dr. Pritam Bhattacharjee and Alak Majumder, “A Variable Delay Circuit to Develop Identical Rise/Fall Time in the Output”, in Computational Advancement in Communication Circuits and Systems, Singapore, 2020.[Abstract]

Circuit designing of variable delay elements has been in practice for decades. However, these delay circuits have not been able to demonstrate equal rise and fall delays at its output. One of the major reasons for this failure is that the construction of delay circuits is non-symmetric. In this paper, we have attempted in designing a simple symmetric architecture which can produce the delayed output with almost identical rise and fall time. The proposed delay circuit is simulated using 90 nm GPDK in Cadence Virtuoso® initially for an input signal of 1 GHz at power supply Vdd\thinspace=\thinspace1.1 V, and the results infer that the contrast (Δ) in rise and fall time is very small even during the input variations.

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2018

D. Sarkar, Dr. Pritam Bhattacharjee, and Alak Majumder, “Data-Dependent Clock Gating approach for Low Power Sequential System”, in MICRO-2018, Bhubaneswar, India (5th International Conference on Microelectronics, Circuits & Systems), 2018.[Abstract]

Power dissipation in the sequential systems of modern CPU integrated chips (CPU-IC viz., Silicon Chip) is in discussion since the last decade. Researchers have been cultivating many low power design methods to choose the best potential candidate for reducing both static and dynamic power of a chip. Though, clock gating (CG) has been an accepted technique to control dynamic power dissipation, question still loiters on its credibility to handle the static power of the system. Therefore in this paper, we have revisited the popular CG schemes and found out some scope of improvisation to support the simultaneous reduction of static and dynamic power dissipation. Our proposed CG is simulated for 90nm CMOS using Cadence Virtuoso and has been tested on a conventional Master-Slave Flip-flop at 5GHz clock with a power supply of 1.1Volt. This assignment clearly depicts its supremacy in terms of power and timing metrics in comparison to the implementation of existing CG schemes.

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2018

Dr. Pritam Bhattacharjee, Bipasha Nath, and Alak Majumder, “LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications”, in International Conference on Electronics, Information, and Communication (ICEIC), 2018.[Abstract]

Power dissipation in integrated circuits is one of the major concerns to the research community, at the verge when more number of transistors are integrated on a single chip. The substantial source of power dissipation in sequential elements of the integrated circuit is due to the fast switching of high frequency clock signals. These signals do not carry any information and are mainly intended to synchronize the operation of sequential components. This unnecessary switching of Clock, during the HOLD phase of either logic 1 or logic 0, may be eliminated using a technique, called Clock Gating. In this paper, we have incorporated a recent clock gating style called LECTOR based clock gating LB CG to drive multi stage architecture and simulated its performance using 90nm CMOS Predictive Technology Model PTM with a power supply of 1.1V at 18GHz clock frequency. A substantial savings in terms of average power in comparison to its non gated correspondent have been observed.

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2017

A. Majumder and Dr. Pritam Bhattacharjee, “Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip”, in 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Bhopal, India, 2017.[Abstract]

With the continuous advent of CMOS, process technologies is extending threat to the noise immune capability of CMOS circuits and the power consumed by them. In present day scenario, though there are a lot of techniques that exist for power reduction, the study of power-supply noise (PSN) based on those techniques is almost unattended in literature. Modern clock gating is one of the best techniques to reduce dynamic and static power dissipation by curbing down the switching activity of the operating clock as well as blocking the direct path between the power lines during logic transition. Therefore, in this paper, we have incorporated gating logic to offer solution to PSN occurrence in CMOS circuits by controlling di/dt, which is generated by the linear current ramp of present day high performance CPU. It is witnessed that, the gated architectures generate very less di/dt with respect to their non-gated counterpart, resulting a noted amount of reduction in PSN.

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2016

Dr. Pritam Bhattacharjee, Sadhu, A., and Das, K., “A register-transfer-level description of synthesizable binary multiplier and binary divider”, in 2016 International Conference on Microelectronics, Computing and Communications (MicroCom), Durgapur, India, 2016.[Abstract]

The paper depicts the RTL (Register Transfer Level) description of Binary Multiplier and Binary Divider. The descriptions are synchronized to the operating clock of the microprocessor. The major operations that get a highlight in this paper is that the multiplier and divider are synthesizable. VHDL (Very High Specific Integrated Circuit - Hardware Description Language) is the language of construct for the design. This work focuses to show that synchronized applications can be implemented at the front-end level of VLSI design methodology.

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2016

Dr. Pritam Bhattacharjee and Majumder, A., “LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder”, in 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Gwalior, India, 2016.[Abstract]

As the chip size is getting decreased with the advent of technology, power dissipation has become a major issue to the circuit designers at the time of designing an integrated circuit. The substantial sources of power dissipation are the static power and dynamic power. A serial adder, one of the vital parts of any processor micro-architecture, is a victim to the huge power flow. In this paper, we have intervened on the solution for controlling both static and dynamic power flow by implementing the LECTOR based clock gating technique on the sequential elements of serial adder. LECTOR helps to reduce the static power by blocking the current between the power lines and gated clock minimizes the dynamic power by eliminating the needless switching of system clock. The simulation is carried out using 32nm, 45nm, 65nm and 90nm Predictive Technology Model and compared the result with Double Gated flip-flop based serial adder.

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2016

Dr. Pritam Bhattacharjee, Majumder, A., and Das, T. D., “A 90 nm leakage control transistor based clock gating for low power flip flop applications”, in 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, United Arab Emirates, 2016.[Abstract]

The continuous growing demand of portable battery-powered electronics devices hunts for Nano-electronic circuit design for ultra-low power applications by reducing dynamic power, static power and short circuit power. In sequential circuit elements of an IC, a notable amount of power dissipation occurs due to the rapid switching of high frequency clock signals, which do not fetch any data bit or information. The needless switching of clock, during the HOLD phase of either logic 1' or logic 0', may be abolished using gated clock. In this paper, we have presented a new clock gating technique incorporating Leakage Control Transistor. The improvised technique is employed to trigger a D-Flip Flop using 90nm PTM technology at 1.1V power supply. We have observed an impressive reduction in power, delay and latency using the proposed gating logic, which has outsmarted the existing works. The simulation is also performed in smaller technology nodes such as 65nm, 45nm and 32 nm to notice the change in delay, dynamic power and static power of the circuit.

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2015

Dr. Pritam Bhattacharjee, Kunal Das, De, M., and De, D., “SPICE Modeling and Analysis for Metal Island Ternary QCA Logic Device”, in Information Systems Design and Intelligent Applications, New Delhi, 2015.[Abstract]

The exploration of work ability of the new trend in quantum dot cellular automata (QCA)–-the ternary QCA, is the major focus in this paper. Both physically and electrically, our tQCA approach is proving its excellence in comparison to the existing binary QCA (bQCA). We also propose a model description for tQCA that will help in determining its logic performances while operating it in the nano computing regime.

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2014

Dr. Pritam Bhattacharjee, Dey, A., Das, K., De, M., and De, D., “Characterization of Ternary Quantum dot cellular Automata for III-V Materials”, in National Conference on Nanoscience and Nanotechnology (NS&NT-2014), 2014.

Publication Type: Journal Article

Year of Publication Title

2020

Dr. Pritam Bhattacharjee, Bidyut K. Bhattacharyya, and Alak Majumder, “A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time”, Circuits, Systems, and Signal Processing, pp. 1-20, 2020.[Abstract]

The design of active delay circuits and variable delay elements is being investigated over the years as they are popular inside the integrated circuit chip, for example in on-chip clock distribution. The function of these kinds of circuit is to transfer the input signal at the output with an added amount of timing delay. For clock signals, it is important to achieve equal rise/fall time in order to support correct level-triggered-based on-chip sequential operation. However, most of the variable delay elements are unable to impart the matching of output rise/fall time. Therefore, in this article, we have unearthed a delay circuit which is expected to generate nearly equal rise/fall time at the output having a unique setup of delivering variable delay. A small-signal model for this proposed circuit is presented to note the related parameters for achieving the near-symmetric output rise/fall time. The circuit has been simulated in Cadence Virtuoso$$^{\textregistered }$$®for 90 nm Process Design Kit with an input signal of 1 GHz at 1.1 V power supply $$(V_{\mathrm{dd}})$$(Vdd). The simulation results assure that the expected functionality of our proposed variable delay architecture is sustained under different corner variations.

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2019

Dr. Pritam Bhattacharjee, Dhiraj Sarkar, and Alak Majumder, “A variation tolerant data dependent clock gating approach for PSN attenuated low power digital IC”, Ain Shams Engineering Journal, vol. 10, pp. 573 - 585, 2019.[Abstract]

The evolution of semiconductor industry has brought in high current flow across the power rails (‘Vdd’ and ground) of digital integrated circuits (IC) encapsulated by the modern chip packages. This instigates the uncontrollable generation of Power Supply Noise (PSN), along with dynamic and static power dissipation across the chip package. There have been several attempts to control this PSN; but it is the clock gating (CG) technique which is found to be efficient for the purpose. Though the primitive CG schemes are effective in managing the dynamic power dissipation, their performance to alleviate the static power and PSN is limited to certain extent. Therefore in this paper, we introduce a new and compact Data-Dependent CG (DD–CG) scheme which can possibly be the savior against both static and dynamic power as well as the PSN. The performance of the new DD–CG is tested over state-of-the-art master–slave flip-flop (MS–FF) and ISCAS’89 benchmark for 90 nm General Process Design Kit (GPDK) technology using the platform of Cadence Virtuoso® at supply voltage of 1.1 V and 5 GHz clock. It is observed that the new DD–CG based MS–FF smartly reduces the PSN individually by 22.19%, 18.99% and 46.92% in contrast to the prior-arts like NC2MOS–CG, LB–CG and no–gated peer. Accordingly, the static power is reduced by 20.63%, 17.79% and 33.61% and the dynamic power is also reduced by 25.14%, 21.24% and 61.57%. To justify the scalability of the design, we have also tested it for the lower process technologies like 65 nm, 40 nm and 28 nm UMC (United Microelectronics Corporation).

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2019

Dr. Pritam Bhattacharjee and Alak Majumder, “A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application”, Journal of Circuits, Systems and Computers, vol. 28, no. 07, p. 1950108, 2019.[Abstract]

Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low-power 8T flip-flop (FF) architecture, which has outsmarted the existing well-known dynamic, semi-dynamic and explicit pulsed flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation based on transmission gate (TG) and pass transistor logic (PTL) as a modification of LECTOR-based gating. These gating logics have proved themselves to be competent enough to reduce both the static and dynamic power dissipations and hence are employed to the proposed flip-flop to achieve further reduction in power than its nongated correspondent. The performance of this proposed gated flip-flop is tested in a finite state machine with its application in low-power serial adder design. All the simulations are carried out using 65-nm and 90-nm CMOS technologies with a power supply of 1.1V at 6.6GHz clock frequency. The gated FF saves 52.12%, 6.36% and 28.18% average power-using LECTOR, TG and PTLs, respectively, with respect to its nongated counterpart in 65-nm technology. The performance metrics of gated and nongated proposed designs are affirmed in the environment of commercialized CMOS foundry.

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2018

Alak Majumder, Dr. Pritam Bhattacharjee, and Das, T. Dhabal, “A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips”, Journal of Circuits, Systems and Computers, vol. 27, p. 1850146, 2018.[Abstract]

As the performing ability of a silicon chip relies on the power supply voltage, it must be configured using genuine power and ground bond pads for mitigating power and ground noise (PGN), which is directly boosted by the increasing peaks of instantaneous current i(t) and current ramp (di/dt). To address the same, a novel and compact clock gating (CG) scheme is unveiled in this paper to effectively control the peak of i(t) and di/dt, thereby subduing PGN. The new CG arrangement is simulated for 90nm Predictive Technology Model (PTM90), where it is observed that the scheme reduces 88.80% of i(t) and 84.19% of average di/dt in comparison to its no gating counterpart along with a reduction of 80.14% in average power dissipation. These results are found to be more prominent when the proposed circuit configuration is tested in 90nm Generic Process Design Kit (GPDK90), proclaiming 88.75% and 84.34% reduction in average di/dt and average power, respectively, to illustrate its capability of truncating PGN in silicon chips.

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2018

Alak Majumder and Dr. Pritam Bhattacharjee, “Variation aware intuitive clock gating to mitigate on-chip power supply noise”, International Journal of Electronics, vol. 105, no. 9, pp. 1487-1500, 2018.[Abstract]

ABSTRACTWith the advent of semiconductor process technology, both the dynamic and static power consumption have become major concerns for the circuit designers. Though clock gating (CG) is a potentially accomplished technique to minimise the dynamic power, it generally fails to cut down the static power dissipation. To address the same, we have unveiled a new CG scheme incorporating leakage control transistor, which simultaneously curbs the static and dynamic power along with the alleviation of power supply noise (PSN) in silicon chips by smartly controlling the current ramp (di/dt) and average current i(t): the main contributors to PSN. The proposed CG does not only save average, dynamic and static power by 84.34%, 90.33% and 66.73%, respectively, but also reduces PSN by 84.44% with respect to its non-gated counterpart when simulated using Cadence Virtuoso® for 90 nm Generic Process Design Kit at a switching frequency of 5 GHz and power supply voltage of 1.1 V.

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2017

Dr. Pritam Bhattacharjee, Alak Majumder, and Bipasha Nath, “A 23.52µW / 0.7V Multi-stage Flip-flop Architecture Steered by a LECTOR-based Gated Clock”, IEIE Transactions on Smart Processing and Computing, vol. 6, no. 3, pp. 220-227, 2017.[Abstract]

Technology development is leading to the invention of more sophisticated electronics appliances that require long battery life. Therefore, saving power is a major concern in current-day scenarios. A notable source of power dissipation in sequential structures of integrated circuits is due to the continuous switching of high-frequency clock signals, which do not carry any information, and hence, their switching is eliminated by a method called clock gating. In this paper, we have incorporated a recent clock-gating style named Leakage Control Transistor (LECTOR)-based clock gating to drive a multi-stage sequential architectures, and we focus on its performance under three different process corners (fast-fast, slow-slow, typical-typical) through Monte Carlo simulation at 18 GHz clock with 90 nm technology. This gating is found to be one of the best gated approaches for multi-stage architectures in terms of total power consumption.

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2017

Dr. Pritam Bhattacharjee, Kunal Das, Dey, A., De, D., and Chakraborty, S., “Estimation of Power Dissipation in Ternary Quantum Dot Cellular Automata Cell”, Journal of Low Power Electronics, vol. 13, no. 2, pp. 231-239, 2017.[Abstract]

The three valued prototype of QCA (Quantum dot Cellular Automata) – ternary QCA or tQCA has become a remarkable paradigm to implement digital logic like the previous prototype of QCA – bQCA. The power dissipation in logic transfer which is an important factor to ascertain the performance of any technology is also important for tQCA and bQCA. Though, estimation of power dissipation in bQCA is quite found in literature, evaluation of power dissipation in tQCA has not made its mark yet. Therefore, in this work we have proposed a novel methodology to estimate power dissipation in tQCA cell during its logic transfer and have also proposed a tQCA electrical model. On testing our tQCA model in SPICE, we have obtained efficient logic transfer from cell to cell within tQCA wire with a very nominal power dissipation of 388.6 fW (femto-watt ~10E-15 watts). The proposed methodology helped us to determine the range of power dissipation in tQCA cell for a particular material at room temperature. Thereby, we could conclude from our obtained results that tQCA technology is quite superior over bQCA in terms of performance.

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2017

Dr. Pritam Bhattacharjee and Kunal Das, “SPICE modeling for Metal Island Charged Confined Cellular Automata”, Journal of Computational and Theoretical Nanoscience, vol. 14, pp. 2326-2331, 2017.[Abstract]

In this work we propose first time a novel design model for Metal Island Charge Confined Cellular Automata (MICCCA) device. The proposed device model operates at room temperature and presents a practical, extremely low power and highly dense nano-device architecture. We also propose a working SPICE model for this device to analyze the phenomenon of electron transport, physical modelling and V –I characteristics. We utilize the efficacy of proposed SPICE model in logic design by simulating a majority voter circuit. Finally, the low power intuition of MICCCA technology is described.

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2016

Dr. Pritam Bhattacharjee, “SPICE Modeling of LDMOSFET Transistor”, Journal of Semiconductor Devices and Circuits ISSN: 2455-3379, vol. 3, no. 1, pp. 42-57, 2016.[Abstract]

High voltage integrated circuits, these days are the most viable alternatives to discrete circuits
for various applications. The popular amongst them is the lateral double diffused MOS
transistor (LDMOS). It is based on the lightly doped drain (LDD) concept. The constraint that
occurred in modeling LDMOS is to minimize the on-resistance along with maintaining a high
breakdown voltage. To achieve the objective, the help of RESURF (Reduced Surface Field)
concept has been taken. In this thesis, a LDMOS based on LDD and RESURF technology has
been designed considering some of the key specific parameters related to LDMOS devices. A
structural, small-signal and electrical model of the device has been stated with Y-parametric
extraction of few device capacitances and the transconductance. With the help of MOS Model
20 (MM20) and TCAD, the current characterization of the device is plotted in the paper.

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2016

Dr. Pritam Bhattacharjee, Dey, A., Kunal Das, Chakraborty, S., and Goswami, R., “Implementation of ternary logic in QCA using SPICE macro-modeling”, Journal of Engineering Technology, vol. 5, pp. 143-155, 2016.[Abstract]

In this paper, we introduce a new trend in Quantum dot Cellular
Automata – Ternary QCA (tQCA) and have justified its presence using
SPICE (Simulation Program with Integrated Circuit Emphasis). The macromodeling which we have shown is concise and compact. Our proposed model
for metal-island tQCA has helped to estimate its logic performance. This
work sets a mark-up in the domain of cellular automata and it has shown that
it can operate in the milli-volt (~60mV) regime.

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2014

Arindam Sadhu, Dr. Pritam Bhattacharjee, and Sabnam Koley, “Performance Estimation of VLSI Design”, Journal of VLSI Design Tools and Technology, vol. 4, no. 2, 2014.[Abstract]

This paper explores performance estimation of VLSI design using simple RC delay model
based an Elmore Delay Method. In this paper Pre-layout & Post-layout VLSI design flow
for delay convergence is also shown.

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2014

A. Sadhu and Dr. Pritam Bhattacharjee, “Methodology of Standard Cell Library Design in .LIB Format”, Journal of VLSI Design Tool & Technology, vol. 4, no. 1, pp. 30-38, 2014.[Abstract]

The importance of standard cell library design methodology is growing with very-large-scale integration (VLSI) technology advancement due to its usage in VLSI EDA synthesis flows. In this paper, to best of our knowledge and information in any published literature no systematic method of standard cell and creating appropriate co-laterals. In this paper the standard cell design methodology, layout topology, methodology for creating characterized timing table has been developed using 250 nm technology GPDK. This method can be easily reused in deep sub-micron technology for appropriate co-laterals. In addition a new methodology of reusing standard cell for full custom design has been proposed in this paper

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2014

Dr. Pritam Bhattacharjee and Arindam Sadhu, “VLSI Transistor and Interconnect Scaling Overview”, Journal of Electronic Design Technology, vol. 5, no. 1, 2014.[Abstract]

In this paper, various types of device and interconnect scaling used for VLSI transistors
are mentioned. Advanced device scaling techniques using SOI & FINFET technology are
discussed for nano-devices. New technologies adopted at research level are stated here in
brief.

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Publication Type: Book

Year of Publication Title

2019

Dr. Pritam Bhattacharjee and Majumder, P. Rana and A., Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges. United Kingdom: IntechOpen Limited, 2019.[Abstract]

The on-chip activities of any modern IC are always inhibited due to the occurrence of power supply noise (PSN) in the chip power line. From many decades, researchers are pondering on what are the major issue of this PSN occurrence and how it can be suppressed without interfering the actual chip functioning. In the course of time, it is found that the uncontrolled triggering of the on-chip system clock and the unguarded on-chip power line is instigating the two major factors for the occurrence of PSN i.e., i(t) → instantaneous current and di/dt → current ramp or the rate of change of current over time. Both i(t) and di/dt are also the sub-factors to rise the PSN components like resistive noise and inductive noise respectively. In this chapter, we light upon the occurrence of resistive and inductive noise as well as depict their individual impact on the PSN occurrences. There is also discussion on how PSN is suppressed over the years in spite of facing challenges in the execution of suppression techniques. This chapter even concludes on the suitable ways for mitigating PSN in the contemporary era of delivering complex on-chip features.

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Publication Type: Patent

Year of Publication Title

2018

Dr. Pritam Bhattacharjee and Alak Majumder, “Voltage Keeper Based Robust Flip Flop For Low Power Applications, Indian Patent File Application No. (Kolkata, India): 201731044358”, 2018.[Abstract]

A D-flip-flop includes a master latch that receives a data input signal and generates a delayed inverted data input signal at a negative-level of a CLOCK signal, and a slave latch that receives the delayed inverted data input signal from the master latch circuit, and generates a further delayed data input signal at a positive level of the CLOCK signal.

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