Citation : Dr. Pritam Bhattacharjee, Alak Majumder, and Bipasha Nath, “A 23.52µW / 0.7V Multi-stage Flip-flo ...
Publisher :IEIE Transactions on Smart Processing and Computing (Scopus)
Citation : Alak Majumder and Dr. Pritam Bhattacharjee, “Variation aware intuitive clock gating to mitigate on ...
Publisher :International Journal of Electronics (SCI/SCIE/Scopus)
Citation : Alak Majumder, Dr. Pritam Bhattacharjee, and Tushar Dhabal Das, “A Novel Gating Approach to Allevi ...
Publisher :Journal of Circuits, Systems and Computers (SCIE/Scopus),
Citation : Dr. Pritam Bhattacharjee and Alak Majumder, “A Variation-Aware Robust Gated Flip-Flop for Power-Co ...
Publisher :Journal of Circuits, Systems and Computers (SCIE/Scopus)
Citation : Dr. Pritam Bhattacharjee, Dhiraj Sarkar, and Alak Majumder, “A variation tolerant data dependent c ...
Publisher :Ain Shams Engineering Journal (SCIE/Scopus)
Citation : Dr. Pritam Bhattacharjee, Arijit Dey, Das, K., Mallika De, and Debashis De, “Characterization of T ...
Publisher :National Conference on Nanoscience and Nanotechnology (NS&NT-2014)
Citation : Dr. Pritam Bhattacharjee, Kunal Das, Mallika De, and Debashis De, “SPICE Modeling and Analysis for ...
Publisher :Information Systems Design and Intelligent Applications (Scopus), Springer India,
Citation : Dr. Pritam Bhattacharjee, Alak Majumder, and Tushar Dhabal Das, “A 90 nm leakage control transisto ...
Publisher :2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) (Scopus), IEEE
Citation : Dr. Pritam Bhattacharjee and Alak Majumder, “LECTOR Based Gated Clock Approach to Design Low Power ...
Publisher :2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), IEEE
Citation : Dr. Pritam Bhattacharjee, Arindam Sadhu, and Kunal Das, “A register-transfer-level description of ...
Publisher :2016 International Conference on Microelectronics, Computing and Communications (MicroCom) (Scopus), IEEE
Citation : Dr. Pritam Bhattacharjee, Bipasha Nath, and Alak Majumder, “LECTOR Based Clock Gating for Low Powe ...
Publisher :International Conference on Electronics, Information, and Communication (ICEIC) (Scopus)
Citation : Alak Majumder and Dr. Pritam Bhattacharjee, “Current Profile Generated by Gating Logic Reduces Pow ...
Publisher :2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) (Scopus), IEEE
Prev