Qualification: 
M.E
e_prabhu@cb.amrita.edu
Phone: 
+91-9994205499

Prabhu E. currently serves as Assistant Professor at the department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore Campus. Prabhu pursued his B. E. degree in Electronics and Communication Engineering from Muthayammal Engineering College, Rasipuram, India, in 2006 and M. E. degree in VLSI Design from Kongu Engineering College, Perundurai, India, in 2008. He is currently pursuing Ph. D. degree in low power arithmetic circuits design area at the Department of Electronics and Communication Engineering, Anna University, Chennai, India.

His research interests include low-power and high-performance arithmetic circuits design, Signal Processing Architectures.  He has served as Technical Program Committee Member in many International Conferences. He is an Associate Member of IETE.

PROFESSIONAL APPOINTMENTS

Year Affiliation
2010 – Present Assistant Professor, Department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore.
2009 – 2010 Assistant Professor, Electronics and Communication Engineering department,  Periyar Maniammai University, Thanjavur, India
2008 – 2009 Lecturer, Electronics and Communication Engineering department, Hindustan University, Chennai, India

Teaching

  • Digital system design
  • VLSI design techniques
  • VLSI Technology
  • Low power VLSI circuits
  • Testing of VLSI circuits
  • Design for test

Publications

Publication Type: Conference Paper

Year of Publication Publication Type Title

2019

Conference Paper

J. Aishvarya, Manindra, P. S. N. V. V., P. Priya, S., Rao, K. Vaseeshwar, and Prabhu E., “Design of Low Power RSC Encoder Using Reversible Logic”, in International Conference on Intelligent Data Communication Technologies and Internet of Things (ICICI) 2018, Cham, 2019.[Abstract]


The principal theme in present world of electronic is low power design. In modern technologies, low power design has drawn significant concern due to increasing transistor counts, higher speed of operations and clock frequencies. Reversible logic plays a vital role when VLSI circuits with minimal power dissipation are considered. It has the ability to decrease the power dissipation by recuperating bit loss from its distinctive one to one mapping. This paper presents a novel design of Recursive Systematic Convolutional (RSC) Encoder using the existing reversible gates. The proposed RSC encoder is coded in Verilog-HDL and synthesized in synopsis DC tool (90 nm library). The power analysis report shows that the proposed RSC encoder circuit dissipates less power when compared to the conventional one.

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2019

Conference Paper

T. A. S. Bhargav and Prabhu E., “Power and Area Efficient FSM with Comparison-Free Sorting Algorithm for Write-Evaluate Phase and Read-Sort Phase”, in Advances in Signal Processing and Intelligent Recognition Systems, Singapore, 2019, vol. 968, pp. 433-442.[Abstract]


In this paper, a comparison-free sorting algorithm is proposed for negative and positive elements which satisfies the conditions such as hardware complexity. The basic idea is to sort the array of input integer elements without performing any comparison related operations between the data. Sorting technique for negative and positive numbers are executed involving similar hardware. Therefore, it doesn't require any complex hardware design. This avoids any usage of memory such as SRAM or any circuitry involving complex design as compared to that of the ones used in other conventional sorting practices. Instead the proposed work utilizes basic registers to store the binary elements. FSM module is proposed with a comparison-free sorting algorithm in order to reduce hardware complexity. All the designs are coded in VHDL and verified using ModelSim SE10.4d simulator. The conventional and the proposed design are synthesized using Vivado and Synopsys DC Design Compiler (90 nm CMOS technology). From the synthesis report, it is observed that proposed FSM with comparison-free sorting algorithm has reduction in power and area compared to the conventional design.

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2018

Conference Paper

V. V. Kavipranesh, Janarthanan, J., Amruth, T. N., Harisuriya, T. M., and Prabhu E., “Power And Delay Efficient Exact Adder For Approximate Multiplier”, in 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2018.[Abstract]


Approximate results are required in many embedded data processors as they reduce time delay and power. As error tolerance adder (ETA) has decreased power drastically trading with accuracy. This work focuses on reducing delay on existing adders when replaced with a fast adder. When compared to the past works on ETA, the proposed work has high power utilization and more accuracy of speed. The proposed design is compared and synthesized for the power and delay. When observed the existing ETA designs, the proposed work achieves significant improvement in power dissipation about 17.13%, 4.6%, 15.4%, 5.35% decrement for 4, 8, 16, 32 bits respectively, and significant improvement in delay about 28.90%, 23.59%, 20.08%, 24.44% decrement for 4, 8, 16, 32 bits respectively.

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2018

Conference Paper

A. Mozhi S. Varman, Baskaran, A. R., Aravindh, S., Prabhu E., and M., K., “Deep Learning and IoT for Smart Agriculture Using WSN”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017, 2018.[Abstract]


Main objective of the smart agricultural system is to improve the yield of the field. In this paper, two main streams are adopted: (i) predicting the suitable crop for the next crop rotation (ii) improvising the irrigation system of the field by selective irrigation. The above goal is achieved by periodically monitoring the field. The monitoring process involves collecting information about the soil parameters of the field. A wireless sensor network (WSN) is established to collect these data and have a hindsight of it by sporadically uploading it to cloud. This uploaded data forms the basis for analytics. Through experimentation, Long Short Term Memory (LSTM) networks is found to be the suitable algorithm. The inferred results are compared with the optimal values and the best-suited crop is intimated to the user through SMS service.

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2018

Conference Paper

A. R. Baskaran, Aravindh, S., Varman, S. A. M., Prabhu E., and M., K., “Smart Energy Meter for Power Grid Using Fuzzy Logic”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017, 2018.[Abstract]


Power stations produce supply at a particular frequency in a given locale. This frequency varies with supply and demand in the grid. This paper mainly focuses on maintaining the optimum frequency in the grid by inducing the users to cope up with the demand by altering the energy's price. With the correlation between the supply-demand, price (for power consumption) is obtained using Fuzzy Logic. The logic is substantiated with simulation through Simulink. The fuzzy logic is then transmuted to Verilog code and is synthesized using Vivado tool. Succeedingly it is implemented in Xilinx Field Programming Gate Array (FPGA).

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2018

Conference Paper

S. Hemalatha and Prabhu E., “An Analysis of Cognitive Radio Spectrum Sensing Methods in Communication Networks”, in 2018 International Conference on Communication and Signal Processing (ICCSP), 2018, pp. 462-467.[Abstract]


The term DSRC which stands for Dedicated Short Range Communication, is a recent technique, that permits high data transmission in conveyance communication. Particularly, FM0 encoding and Manchester encoding schemes are adopted for DSRC standards to obtain dc balance and ensure reliability of signal. Regardless, the code variance between FM0 and Manchester restricts the designer to design a fully reusable DSRC Encoder. To overcome this limitation, Similarity Oriented Logic Simplification technique was proposed, which will result in improving the hardware utilization rate to 100% so that power and area can be reduced. Radio Frequency Identification [RFID] technology is one of the noteworthy converging technologies in this era. They are used in many fields including Logistics and Supply Chain, Race timing, Library system and so on. RFID technology can be implemented with Intelligent Transportation System, to make it applicable in Electronic Toll Collection system. For accommodating RFID in DSRC system, Miller encoding technique should be incorporated in this architecture. Miller encoding is widely used for encoding higher frequency radio signals. This project deals with the two types of encoding schemes such as FM0 and Manchester encoding that is used code the DSRC information and again encode it with miller codes for RFID communications.

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2017

Conference Paper

N. Krishna, Murugappan, V., Harish, R., Midhun, M., and Prabhu E., “Design of a Novel Reversible Nlfsr”, in 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2017.[Abstract]


Reversibility is among the rapidly evolving areas of system design, where the design has ideally zero power dissipation. Considerable research and designs have been developed in this field and the recent designs of MACs (Multiplier and Accumulators) and memory elements in reversible logic are still a budding field of research. Reversible logic is a very promising choice for quantum computational systems, DNA computation and other Low Power digital system designs. Here, we propose three novel reversible Non-Linear Shift Register (NLFSR) designs. The proposed designs are implemented and compared in terms of area and power with a conventional non-reversible NLFSR design using the Synopsys Design Compiler Tool and ModelSIM Quartus 6.5. The proposed novel designs give a considerable reduction in switching power, when compared with the conventional design.

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2016

Conference Paper

D. K. Kartik, Prabhu E., and Nithin, S., “Frequency Estimation of Power System Using CMAC Artificial Neural Network”, in 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT), 2016.[Abstract]


The power system frequency plays more important role in power system and the paper intends a different technique to estimate exact power system frequency of a distorted sinusoid wave. The estimation of frequency is articulated as optimization problem, and it aims to reduce the estimation error. And the problem statement is executed in soft computing technique CMAC Artificial Neural Network (ANN). The algorithm is implemented and performance is simulated.

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2016

Conference Paper

R. Balakumaran and Prabhu E., “Design of high speed multiplier using modified booth algorithm with hybrid carry look-ahead adder”, in Proceedings of IEEE International Conference on Circuit, Power and Computing Technologies, ICCPCT 2016, 2016.[Abstract]


In this paper novel method for multiplier and accumulator is proposed by combining reversible logic functions and hybrid carry look-ahead adder. Modified booth algorithm produces less delay in comparison with a normal multiplication process and it also moderates the number of partial products. The Carry look-ahead adder is used for controlling the overall MAC delay. The main purpose of designing a reversible logic is to reduce the circuit complexity, power consumption and loss of information. Here we survey on possible ways to make a full adder design using different reversible logic gates. We also proposed a new hybrid CLA from the existing hierarchical CLA which exhibits high performance in terms of computation, power consumption and area. Area, delay and power complexities of the resulting design are reported. The proposed MAC shows better performance compare to conventional method and has advantages of reduced area overhead and critical path delay. This new high speed hybrid carry look-ahead adders are simulated and synthesized using Synopsys (90 nm) Design Compiler and Xilinx ISE simulator.

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2014

Conference Paper

P. R. Gokul, Prabhu E., and Mangalam, H., “Performance comparison of multipliers based on Square and Multiply and montgomery algorithms”, in Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on, 2014.[Abstract]


Modular multiplication is the core arithmetic for most of the Cryptographic applications. Montgomery multiplication is one of the fastest methods available for performing modular multiplication. A k - partition method for Montgomery multiplication is thoroughly studied and analysed. This method reduces the time complexity of multiplication from O (n) to O (n/k). Another method for modular exponentiation - Square and Multiply method is implemented. As the name suggests, squaring is the main principle behind this method. The implementation results are compared with that of an ordinary Montgomery multiplier and the k - partition method in terms of power and area constraints. Results for 128, 256, 512 and 1024 bit input operands show that the Square and Multiply method is more power efficient than the other two More »»

Publication Type: Journal Article

Year of Publication Publication Type Title

2019

Journal Article

S. P. Lakshmi Narayan, Kavinkartik, E., Prabhu E., ,, ,, D., C., O., M., and K.-C., L., “IoT Based Food Inventory Tracking System”, Communications in Computer and Information Science, vol. 968, pp. 41-52, 2019.[Abstract]


A key component in effective kitchen management is inventory control. Keeping track of the kitchen inventory leads to more informed planning and decision-making. With technology advancing in a fast pace and everything around us becoming automated, people prefer to monitor and perform their day-to-day activities by using the smart devices they carry everywhere rather than manually recording and monitoring things. Maintaining and keeping track of everyday common food inventory is becoming one of the major problems in various households, restaurants and food chains. Replenishing the containers at the right moment and also knowing the expiry of foods is a major concern. Working people and busy restaurants find it difficult to keep track because it requires human intervention at the right time. Through this, it is easy to keep an eye on potential problems related to waste and pilferage. In this project we propose an IOT (Internet of Things) based food inventory tracking system, which ensures real time monitoring of the kitchen inventory. The collected data can be analysed in real time to understand the daily or weekly consumption and also predict usage/consumption patterns. There is also provision to check the real time status, history of consumption through an android application. The system contains a Microcontroller, load cell and wireless Module, MQTT broker, a desktop application and an Android application through which real time inventory tracking is performed. The proposed solution is completely wireless and reliable for both domestic and commercial purposes.

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2016

Journal Article

Prabhu E. and Mangalam, H., “Power Optimized Vedic Parallel MAC Unit: GDI Technique”, Asian Journal of Information Technology, vol. 15, no. 16, pp. 2954-2957, 2016.[Abstract]


In vedic mathematics of the sixteen algorithms, Urdhva Tiryakbhyam is identified as one among the efficient algorithms for multiplication in terms of delay, power and area. In this study, a parallel MAC unit has been developed which employs compressor based Urdhva Tiryakbhyam multiplier for its operation. Transistor level power optimization is realized by Gate Diffusion Input (GDI) Technique using Synopsys HSPICE. The main advantage of the proposed technique is use of less number of transistors, result in reduced power consumption. The experimental results indicate an absolute reduction in total power consumption by 39 and 34.2% for 4-bit and 8-bit MAC, respectively when compared to standard CMOS technique.

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2016

Journal Article

Prabhu E., Mangalam, H., and Karthick, S., “Design of area and power efficient Radix-4 DIT FFT butterfly unit using floating point fused arithmetic”, Journal of Central South University, vol. 23, pp. 1669-1681, 2016.[Abstract]


In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time (DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design. More »»

2015

Journal Article

Prabhu E. and S, J., “Parallel multiplier-accumulator unit based on Vedic mathematics”, ARPN Journal of Engineering and Applied Sciences, vol. 10, 2015.[Abstract]


In this paper, an efficient parallel multiplier and accumulator (MAC) unit based on Vedic mathematics is presented. Vedic mathematics utilizes the Urdhva-tiryagbhyam sutra for the multiplier design. The proposed MAC architecture enhances the speed of operation while reducing the gate area and power dissipation. We also achieve improved delay with the help of Vedic encoder followed by the removal of accumulator stage by parallelizing the intermediate results feeding the input. Such pipelining of the midway results, prior to the final adder, has the effect of combining the accumulator stage with the partial product stage of the multiplier. Further, the overall computation speed of MAC unit is elevated by the efficient use of higher order compressors in the merged partial product compression and accumulator (PPCA) architecture. The area, timing and power reports show that, the critical path delay of the proposed design is significantly reduced and it outperforms the existing designs. We report an absolute improvement of 20-30% and 7-18% respectively for the 4-bit and 8-bit Vedic MAC units, in terms of its total circuit power, critical path delay and cell area. The architecture was synthesized using standard 90nm CMOS library and implemented on Altera's Cyclone II series FPGA. More »»

2015

Journal Article

Prabhu E. and Reddy, B. Madhukar, “An Efficient 16-Bit Carry Select Adder With Optimized Power and Delay”, International Journal of Applied Engineering Research, vol. 10, 2015.[Abstract]


Design of electronic devices is very important to reduce power, delay and area of components because these factors are impact the quality and performance of devices. Adder is most fundamental and important device in microprocessors and DSP chips Carry Select Adder (CSA) is the finest adder of choice while considering the need for high speed arithmetic designs. Previous architectures i.e., Conventional CSA and Binary to Excess-1 Converter (BEC) based Square Root Carry Selected Adder (SQRT-CSA) clearly explained. The redundancies in logic operations and dependencies of data factors are effects the power, area and delay in any adder design. The analysis of BEC-based SQRT-CSA (BEC SQRT-CSA) clearly shows the possibility to reduce the power and area by proper modifications at gate-level architecture because this design has been effected by above factors. This work reduces the redundancy in logic operations by introducing a new adder instead of the conventional BEC. The proposed design generates the sum and carry signals for both carry input signals (Cin =0 and Cin =1) for n-number of bits using n-number of new adder. The proposed new adder implemented with less number of logic gates compared with Half Adder (HA). the proposed CSA has less power consumption of 1.5%,44.21%,54.77%, and low area of 6.2%,21.2%,31.4% for 4,8,16-bit respectively compared to BEC SQRT-CSA. More »»

2015

Journal Article

Prabhu E., I, V. R., R, D. Udhayan, S, R., P, W. Thadeus, and S, A., “Design and implementation of digital household energy meter with a flexible billing unit using FPGA”, International Journal of Applied Engineering Research, vol. 10, pp. 28331-28340, 2015.

2015

Journal Article

S. Karthick, Valarmathy, S., and Prabhu E., “Low power systolic array based digital filter for DSP applications”, Scientific World Journal, vol. 2015, 2015.[Abstract]


Main concepts in DSP include filtering, averaging, modulating, and correlating the signals in digital form to estimate characteristic parameter of a signal into a desirable form. This paper presents a brief concept of low power datapath impact for Digital Signal Processing (DSP) based biomedical application. Systolic array based digital filter used in signal processing of electrocardiogram analysis is presented with datapath architectural innovations in low power consumption perspective. Implementation was done with ASIC design methodology using TSMC 65 nm technological library node. The proposed systolic array filter has reduced leakage power up to 8.5% than the existing filter architectures. © 2015 S. Karthick et al.

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2014

Journal Article

S. Karthick, Valarmathy, S., and Prabhu E., “Low Power Heterogeneous Adder”, International Journal of Applied Engineering and Research, vol. 9, no. 22, pp. 13449-13464, 2014.[Abstract]


Flexibility and Portability has increased the requirement of Low Power components in fields like multimedia, signal processing and other computing applications. Adders are the essential computing elements in such applications. However the present adder architectures with hybrid/heterogeneous features provide performance variations but limits to consume less power. In this paper, low power heterogeneous adder architecture is proposed to enable flexibility to the computing applications and consume less power. 128 bit heterogeneous adder architecture is built using three low power sub-adders (ripple carry, carry look a head and carry bypass adders). Adder variants in sub-adders block of heterogeneous adder architecture enables to select required quality metrics viz., area, timing and power, for the design. Application requirements like low power – same performance, low power – low area, variable performance can be selected. Designs are demonstrated using Verilog HDL by synthesizing with Cadence’s RTL Compiler and mapped to TSMC 65nm technological library node. More »»

2013

Journal Article

Sa Karthick, Valarmathy, Sa, and Prabhu E., “Reconfigurable fir filter with radix-4 array multiplier”, Journal of Theoretical and Applied Information Technology, vol. 57, pp. 326-336, 2013.[Abstract]


FIR filters are commonly used digital filters which find its major application in digital signal processing. In conventional FIR filter, the input vector form is delayed by one sample and then multiplied with filter coefficients which are subsequently accumulated by the adders. The drawbacks due to this are high device utilization and high power consumption. In order to compensate these drawbacks, we propose a reconfigurable FIR filter using radix-4 multiplier. The major changes in the proposed system are radix-4 multiplier for multiplication and change in the basic architecture of the FIR filter. In this method, we combine all the input tap values having similar co-efficient values and then multiplying those with the respective co-efficient. The proposed design is simulated and synthesized using Xilinx. The proposed method is compared with the existing FIR filter. From the results, it is observed that our proposed method has got better results by having less number of occupied slices and low power consumption. The power analysis report of a 8-tap FIR filter using the proposed approach consumes 60μW at 25MHz, 110μW at 50MHz, 170μW at 75MHz and 220μW at 100MHz compared with the existing approach which was implemented on Spartan-3E. Additionally, the proposed design was also tested for n-tap FIR filter implemented in Virtex-4 FPGA and compared with the existing technique, which shows that our approach minimizes the number of slices occupied by the design and reduces the power consumption. © 2005 - 2013 JATIT & LLS. All rights reserved.

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2013

Journal Article

Prabhu E., Mangalam, H., and Karthick, S., “A low power multiplier using encoding and bypassing technique”, Journal of Theoretical and Applied Information Technology, vol. 57, pp. 251-260, 2013.[Abstract]


In this paper, a low power Encoding and Bypassing technique based shift-add multiplier is presented. The proposed architecture is derived from simple way to reduce power consumption and area of the multiplier in VLSI design architecture level model. The proposed architecture maximum reduces the power consumption and area compared to the other conventional multiplier. The modification to the multiplier includes proposed Encoder design for Modified Radix-4 recording rules, removal of zero partial products using bypassing technique (decoder). A decoder instead of bypass and feeder register is utilized for the removal of zeros (bypassing) and selecting the current partial product value to be stored in register. In this paper, encoder and decoder selector circuit has been used in the proposed model work. Low power consumption and low area occupied multiplier architecture model is proposed. The simulation result for the encoding process and bypassing technique using decoder generated using Xpower analyzer in Xilinx 10.1 ISE (integrated software environment) represents the dynamic power consumption is reduced to almost 50%. When the power consumed by the proposed multiplier using Spartan-2 is 6.28mW, the Virtex-4 device is 6.89mW. The proposed multiplier is mainly applicable for designing low power VLSI circuits and high speed switching techniques. © 2005 - 2013 JATIT & LLS. All rights reserved.

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Publication Type: Conference Proceedings

Year of Publication Publication Type Title

2014

Conference Proceedings

R. M, Prabhu E., and H, M., “A versatile low power design of bit-serial multiplier in finite fields GF (2m)”, Communications and Signal Processing (ICCSP), 2014 International Conference on. pp. 748-752, 2014.[Abstract]


A novel and efficient architecture for a versatile polynomial basis multiplier over GF(2m) is dealt with. The value m; of the irreducible polynomial degree, can be changed and so the multiplier can be configured and programmed. Thus versatility of the multiplier refers to its reconfigurable property. The architecture deals with an efficient execution of the Most Significant Bit (MSB)-First, bit serial multiplication for different operand lengths. The attractive features of the proposed architecture are (a) its flexibility on arbitrary Galois field sizes, (b) its hardware simplicity which results in small area implementation, (c) Low power consumption by employing the gated clock technique, power gating and Multi Vth optimization techniques (d) improvement of maximum clock frequency due to the lessening of critical path delay. More »»