Publication Type : Journal Article
Publisher : Asian Journal of Information Technology
Source : Asian Journal of Information Technology, Volume 15, Issue 16, p.2954-2957 (2016)
Url : http://docsdrive.com/pdfs/medwelljournals/ajit/2016/2954-2957.pdf
Campus : Chennai
School : School of Engineering
Department : Electronics and Communication
Year : 2016
Abstract : In vedic mathematics of the sixteen algorithms, Urdhva Tiryakbhyam is identified as one among the efficient algorithms for multiplication in terms of delay, power and area. In this study, a parallel MAC unit has been developed which employs compressor based Urdhva Tiryakbhyam multiplier for its operation. Transistor level power optimization is realized by Gate Diffusion Input (GDI) Technique using Synopsys HSPICE. The main advantage of the proposed technique is use of less number of transistors, result in reduced power consumption. The experimental results indicate an absolute reduction in total power consumption by 39 and 34.2% for 4-bit and 8-bit MAC, respectively when compared to standard CMOS technique.
Cite this Research Publication : Prabhu E. and Mangalam, H., “Power Optimized Vedic Parallel MAC Unit: GDI Technique”, Asian Journal of Information Technology, vol. 15, no. 16, pp. 2954-2957, 2016.