Qualification: 
M.E
Email: 
sr_ramesh@cb.amrita.edu
Phone: 
+91- 9894391731

Ramesh S. R. currently serves as Assistant Professor at the department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore Campus. He joined Amrita Vishwa Vidyapeetham in July 2007. Ramesh completed his Master of Engineering in VLSI Design from Arulmigu Kalasalingam College of Engineering (Anna University, Chennai ) in 2007 and Bachelor of Engineering in ECE from Cape Institute of Technology (Anna University, Chennai) in 2005. He is an Associate Member in IETE. 

Research Expertise

  • Pursuing Ph.D in the field of VLSI Timing Analysis from Anna University, Chennai
     

PG Projects

  • Analytical Modeling of Logic Resource Utilization for Early Stage FPGA Architecture Development
  • Statistical Static Timing Analysis Using Parallel Processing of Timing  Graphs
  • Design And Implementation of 1D Discrete Multiwavelet Transform For Infrasound Classification
  • Statistical Timing Analysis Using Probabilistic Approaches
  • Decomposition And Synthesis of XOR Based Logic Circuits For LUT Based FPGAs
  • Probabilistic Activity Estimator For4-input LUT Based FPGA Circuits
  • Data Flow Transformation for Optimization of Digital/DSP Circuits
  • Design of an Optimized Double Precision Floating Point Divider Using Cache Memory and a Multiplier
  • FPGA Implementation of Low Density Parity Check Code Decoder

UG Projects

  • A Comparative analysis on Static and Statistical Timing Techniques
  • An Efficient FIR Filter Design Using Common Sub Expression Elimination Method
  • Multimode Floating Point Adder and Multiplier
  • Power Estimation of Combinational Circuits Using Spatial Correlation
     

Teaching

  • Electronic Circuits
  • VLSI Technology
  • VLSI Design
  • Linear Integrated Circuits
  • Static Timing Analysis
  • Solid State Devices
  • Semiconductor Memory Design
  • Electronic System Level Design and Verification
     

Publications

Publication Type: Journal Article

Year of Conference Publication Type Title

2015

Journal Article

Ramesh S. R. and Jayaparvathy, R., “Probabilistic activity estimator and timing analysis for LUT based circuits”, International Journal of Applied Engineering Research, vol. 10, pp. 33238-33242, 2015.[Abstract]


Low power VLSI has received tremendous attention due to power constraints in designs. This paper details a survey on switching activity estimation techniques. It also presents a computationally efficient activity estimator which is probabilistic in nature. This estimator is faster and accurate. Simulation based approach is practically impossible for large circuits. More statistical parameters related to activity estimation are incorporated to improve the accuracy. This methodology is implemented on MCNC benchmarks. LUT mapping is done using the logic synthesis tool ABC. Spatial correlation is considered by computing the activities at each LUT. Power estimation using Synopsys Design Compiler tool gave 18% reduction in dynamic power for optimized circuits. Timing analysis plays an important role in circuit design. Statistical Timing Analysis (STA) is performed and the delay analysis is obtained. An effective tradeoff between timing and power were reported. © Research India Publications.

More »»

2015

Journal Article

P. L. Paleri and Ramesh S. R., “Early Stage FPGA Architecture Development by Exploiting Dependence on Logic density”, International Journal Of Applied Engineering Research, vol. 10, no. 11, pp. 28889-28902, 2015.

2014

Journal Article

B. P. J and Ramesh S. R., “A Survey of SSTA Techniques with Focus on Accuracy and Speed”, International Journal of Computer Applications, vol. 89, no. 7, pp. 21-25, 2014.[Abstract]


Timing analysis plays a vital role in chip design, which analyze whether a chip design meets the timing constraints. The main objectives of timing analysis are speed and accuracy. There are two engines for timing analysis namely Statistical Timing Analysis (STA) and Statistical Static Timing Analysis (SSTA). VLSI CAD has been gaining a lot of interest in both STA and SSTA. As technology continues to advance deeper in to the nanometer regime, a tight control on the process parameters is increasingly difficult. To account these process parameters which are probabilistic in nature while performing timing analysis SSTA is preferred. The main goal of SSTA is to improve the accuracy without any reduction in speed by considering process variations. This paper presents a survey of SSTA approaches and techniques for improving accuracy and speed by considering the topological correlations and spatial correlations. More »»

2012

Journal Article

A. P.V and Ramesh S. R., “An Approach towards Logic Synthesis by Functional Decomposition”, International Journal of Engineering Research and Applications , vol. 2, no. 3, pp. 324-330, 2012.[Abstract]


This paper surveys some of the basic principles behind logic synthesis. A few methods of logic synthesis are also discussed. Functional decomposition is an efficient technique for synthesis of logic circuits targeted on Look Up Table based FPGAs. It decomposes any circuit into a network of sub circuits. A method of functional decomposition for single output XOR based circuits is presented. It utilizes Gauss Jordan elimination, a method based on linearity, to decompose the circuits. The method was tested on a set of MCNC benchmark circuits in Blif format, and was successful in decomposing circuits efficiently. In case of XOR based circuits, the XOR relationship between the different sub circuits can be exposed by this method. A reduction in area was obtained due to this in case of large XOR based circuits and hence can be used for area driven logic synthesis. More »»

2012

Journal Article

Ramesh S. R. and .P.J, A., “Toggle Rate Estimation Technique for 4-Input LUT based FPGA Circuits”, International Journal of Engineering Research and Applications , vol. 02, no. 3, pp. 198-203, 2012.[Abstract]


Power dissipation of a VLSI chip was not a concern in the past. A lot of effort has been put into synthesis for speed and area, power optimization has been explored only recently. Since power estimation is the foremost step in any low power design; this work concentrates on developing a technique that estimates the toggle rates for circuits implemented on a 4-input LUT based FPGA using probabilistic technique. The aim of this work is to develop a toggle rate estimation technique with improved accuracy by incorporating the effects of correlation of logic signals and glitches. This approach is tested on a set of MCNC circuits. The ABC logic synthesis system is used for LUT mapping.

More »»

Publication Type: Conference Paper

Year of Conference Publication Type Title

2014

Conference Paper

B. P. J and Ramesh S. R., “A comparison on timing analysis using probabilistic approaches”, in Communications and Signal Processing (ICCSP), 2014 International Conference on, 2014.[Abstract]


This paper presents a comparison on various timing analysis methods. Timing analysis is a critical step in any digital integrated circuits. Static timing analysis is a method to validate the timing performance of a digital circuit without requiring simulation. Technology and the process scaling to nanometer regime have lead to significant increase in process variations. These variations are needed to incorporate in static timing analysis. In the proposed method the delays of the gates and the arrival time are modeled by probabilistic distributions. The gate delays and the arrival time are modeled by using the operations statistical convolution integration and the statistical maximum. The delay values used is extracted from the standard delay format file for each gate. The method is tested by using various ISCAS benchmark circuits. Further statistical static timing analysis with arrival time at 3σ points away from the mean is calculated. The statistical static timing analysis results are found to be more accurate as it considers process variations. More »»

2012

Conference Paper

Ramesh S. R. and P.V, A., “Area and speed aware Decomposition of Logic circuits for Look Up Table based FPGAs”, in Third International Conference on Intelligent Information Systems and Management(IISM), RVS College of Engineering and Technology, Coimbatore, 2012.

2010

Conference Paper

A. Baby, Raju, R., and Ramesh S. R., “Cross talk Effects on Mixed Signal CMOS ICs”, in International Conference on Advances in Information Communication Technology and VLSI Design , 2010.

2010

Conference Paper

S. .K and Ramesh S. R., “Design and Implementation of an Optimized Double Precision Floating Point Divider using Cache Memory”, in International Conference on Embedded Systems (ICES 2010) , EEE Department, Coimbatore Institute of Technology, Coimbatore, 2010.

2010

Conference Paper

M. .B and Ramesh S. R., “Online Noise Reduction Technique for Mobile Communication Using LABVIEW”, in International Conference on Embedded Systems (ICES) , by EEE Department, Coimbatore Institute of Technology, Coimbatore , 2010.

Publication Type: Conference Proceedings

Year of Conference Publication Type Title

2014

Conference Proceedings

Ramesh S. R., priya.V, S., Reddy, N. S., Mogi, V. M. Abitha, and .S.Sakthi, K., “An Efficient FIR Filter Design using CSE Method”, International Conference on Intelligent Engineering Systems . Department of ECE, Easa College of Engineering and Technology, Coimbatore., 2014.

2012

Conference Proceedings

P. Ja Anju and Ramesh S. R., “Toggle rate estimation technique for FPGA circuits considering spatial correlation”, 2012 3rd International Conference on Computing, Communication and Networking Technologies, ICCCNT 2012. Coimbatore, Tamilnadu, 2012.[Abstract]


The interest in low power chips and systems are driven by both business and technical needs. Since power estimation is the foremost step in any low power design, this work concentrates on developing a technique that estimates the toggle rates for circuits implemented on a 4 input LUT based FPGA. Basically there are two methods of power estimation namely simulation based and probabilistic approach. Simulation based approach is more accurate that the later, but this method is computationally very expensive, practically impossible for large circuits. So, probabilistic method is a solution for this problem. They require only one time simulation and hence they are faster. This advantage is available at the cost of loss of accuracy. So this work focuses on improving the accuracy of probabilistic approach by incorporating more statistical parameters related to toggle rate estimation. This approach is tested on a set of MCNC circuits. The ABC logic synthesis system is used for LUT mapping. This method does a power modeling of FPGA circuits under spatial correlation by computing the transitions at each LUT by processing them in topological order. Gate Delays are also considered in this approach. © 2012 IEEE.

More »»

2011

Conference Proceedings

Ramesh S. R., Dr. Bala Tripura Sundari B., and .N, N., “Dataflow Transformation for Optimization of Digital/DSP Circuits”, Third National Conference on Recent Trends in Communication, Computation & Signal Processing organized by Department of ECE,Amrita School of Engineering, Ettimadai . 2011.

2010

Conference Proceedings

S. Manojna.D, .S, S. S., and Ramesh S. R., “VLSI Implementation of Asynchronous CDMA using Matched Filter”, International Conference on Communication and Computational Intelligence. 2010.

2010

Conference Proceedings

Ramesh S. R., Scaria, A., and Nath.D, B., “A Systolic Architecture for Efficient Colour to Grey Scale Conversion and Reconstruction”, International Conference on Emerging Trends in Signal Processing and VLSI Design. Department of ECE, Guru Nanak Engineering College, Ibrahimpatnam., 2010.

2010

Conference Proceedings

Ramesh S. R. and .K, S., “Design of an Area Optimized Double Precision Floating Point Divider on FPGA”, International Conference on Intelligent Information Systems & Management-(IISM10). RVS College of Engineering and Technology, Coimbatore, 2010.

2010

Conference Proceedings

M. .B and Ramesh S. R., “Speech CODEC for Single Channel Applications Using LABVIEW”, Second National Conference on Recent Trends in Communication, Computation & Signal Processing(RTCSP2010). Department of ECE, Amrita School of Engineering , Ettimadai, 2010.

2010

Conference Proceedings

Ramesh S. R., .S.M, L., and .T, A., “On-chip FPGA Implementation of OFDM Receiver Components”, First International Conference on Emerging Trends in Signal Processing and VLSI Design. Department of ECE, Guru Nanak Engineering College, Ibrahimpatnam, 2010.

2009

Conference Proceedings

R. .S and Ramesh S. R., “FPGA Implementation of a Low Density Parity Check Code Decoder using Min Sum Algorithm”, National Conference on Emerging trends in Communication Engineering. Department of ECE, Trichy Engineering College, Trichy, 2009.

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