Qualification: 
M.E
sr_ramesh [at]cb[dot]amrita[dot]edu
Phone: 
+91- 9894391731, +91 422 2685000 Ext. 5731

Ramesh S. R. completed Master of Engineering in VLSI Design from Arulmigu Kalasalingam College of Engineering (Anna University, Chennai) in 2007 and Bachelor of Engineering in Electronics and Communication Engineering from Cape Institute of Technology (Anna University, Chennai) in 2005. He joined as a Lecturer with the Department of Electronics and Communication Engineering, Amrita Vishwa Vidyapeetham in July 2007.Currently he is serving as an Assistant Professor (Sr.Gr) in the same department.

He is pursuing Ph.D in the area of VLSI Timing Analysis from Anna University, Chennai. His areas of interest include VLSI Design, Static Timing analysis, VLSI CAD, FPGA Logic Architectures and Embedded Sensor Networks. He has published more than 20 scientific papers in reputed journals and conferences. He has served as a reviewer for various journals and international conferences He is an Associate Member in IETE.

Education

  • Pursuing: Ph. D. in VLSI
    Anna University, Chennai
  • 2007: M. E. in VLSI
    Anna University, Chennai/ Arulmigu Kalasalingam College of Engineering

Professional Experience

Year Affiliation
July 2011 to till date Assistant Professor (Sr. Gr), Amrita Vishwa Vidyapeetham
Domain : Teaching, Research
July 2009 to June 2011 Assistant Professor, Amrita Vishwa Vidyapeetham
Domain : Teaching, Research
July 2007 to June 2009 Lecturer, Amrita Vishwa Vidyapeetham
Domain : Teaching

Academic Responsibilities

SNo Position Class / Batch Responsibility
1. Batch Coordinator 2015-19 Coordinating class Advisers for smooth conduct of academics
2. Class Adviser 2015 – 19 EIE Monitoring Students and counseling
3. Mentor Open Lab 2017-18 Third Year ECE and EIE Facilitates hardware prototyping and arrangement of resources
4. Project Coordinator 2018-19 Final Year ECE and EIE Coordinating class Advisers for conduct of project reviews

Undergraduate Courses Handled

  1. CMOS Integrated Circuits
  2. Electronics Engineering
  3. Electronic Circuits
  4. VLSI Design
  5. VLSI Technology
  6. Linear Integrated Circuits

Post-Graduate / PhD Courses Handled

  1. Solid State Devices (VLSI Design)
  2. CAD for VLSI (VLSI Design)
  3. Micro Electromechanical Systems (VLSI Design)
  4. Static Timing Analysis (VLSI Design)
  5. Analysis and Design of Mixed Signal VLSI Circuits (VLSI Design)
  6. VLSI Fabrication Technology (VLSI Design)

Participation in Faculty Development / STTP / Workshops /Conferences

SNo Title Organization Period Outcome
1. Author Workshop on “scholarly writing and publishing” ASE,Ettimadai April 11, 2018 Research
2. ISTE STTP on CMOS, Mixed Signal and Radio Frequency VLSI Design IIT Kharagpur January 30 – February 4, 2017 Course Plan development for PG
3. National workshop on Signal and Image processing Applications using Xilinx system generator ASE,Ettimadai April 10 - 11, 2014 Research
4. Research Seminar on Emerging Perspectives in Nanoelectronics R&D ASE,Ettimadai September 19, 2014  Research
5. ISTE workshop on Analog Electronics IIT Kharagpur June 4 -14, 2013 PG Elective course
6. Workshop on Research and Project Areas in VLSI Design ASE,Ettimadai January 25, 2013 Research
7. ISTE workshop on Writing Effective Conference Papers IIT Bombay February 18 - 19, 2012 Research
8. Mission 10X workshop ASE & Wipro December 20 - 24, 2010 Innovative Teaching
9. Pre-Conference workshop on Embedded Systems Coimbatore Institute of Technology July 13, 2010 Research
10. Course on Nanotechnology ASE , Ettimadai July 13, 2009 Research
11. Workshop on UltraSparc T2 Processor microarchitecture Sun Microsystems March 29 - 30, 2008 Research
12. Workshop on Optical Communication and Network Design and Modeling Coimbatore Institute of Technology February 4, 2008 Research

Organizing Faculty Development / STTP / Workshops /Conferences

SNo Title Organization Period Outcome
1. National Conference on Recent Trends in Communication and Signal Processing RTCSP’09 ASE , Ettimadai April 7, 2009 Research
2. Student Project Contest ASE ,Ettimadai February 29, 2008 Practical knowledge and Innovation

Academic Research – PG Projects

SNo Name of the Scholar Programme Specialization Duration Status
1. Akella Krishna Vamsi VLSI Design Low Power VLSI 2018-19 Ongoing
2. LachiReddy Dhanunjay VLSI Design Low Power VLSI 2018-19 Ongoing
3. Nithya J VLSI Design Low Power VLSI 2018-19 Ongoing
4. Kosanam Manikanth VLSI Design Static Timing Analysis 2017-18 Completed
5. Mukkamala Venkata Durga Pavan VLSI Design Low Power VLSI 2017-18 Completed
6. Sreenath K VLSI Design Static Timing Analysis 2016-17 Completed
7. Haritha H VLSI Design Low Power VLSI 2016-17 Completed
8. Samarshekar R VLSI Design Static Timing Analysis 2015-16 Completed
9. Prem Lal Paleri VLSI Design VLSI CAD 2014-15 Completed

Research Expertise

  • Pursuing Ph.D in the field of VLSI Timing Analysis from Anna University, Chennai

PG Projects

  • Analytical Modeling of Logic Resource Utilization for Early Stage FPGA Architecture Development
  • Statistical Static Timing Analysis Using Parallel Processing of Timing  Graphs
  • Design And Implementation of 1D Discrete Multiwavelet Transform For Infrasound Classification
  • Statistical Timing Analysis Using Probabilistic Approaches
  • Decomposition And Synthesis of XOR Based Logic Circuits For LUT Based FPGAs
  • Probabilistic Activity Estimator For4-input LUT Based FPGA Circuits
  • Data Flow Transformation for Optimization of Digital/DSP Circuits
  • Design of an Optimized Double Precision Floating Point Divider Using Cache Memory and a Multiplier
  • FPGA Implementation of Low Density Parity Check Code Decoder

UG Projects

  • A Comparative analysis on Static and Statistical Timing Techniques
  • An Efficient FIR Filter Design Using Common Sub Expression Elimination Method
  • Multimode Floating Point Adder and Multiplier
  • Power Estimation of Combinational Circuits Using Spatial Correlation

Teaching

  • Electronic Circuits
  • VLSI Technology
  • VLSI Design
  • Linear Integrated Circuits
  • Static Timing Analysis
  • Solid State Devices
  • Semiconductor Memory Design
  • Electronic System Level Design and Verification

Publications

Publication Type: Journal Article

Year of Publication Title

2018

K. Sreenath and Ramesh S. R., “Statistical Viability Analysis and Optimization through Gate Sizing”, Lecture Notes in Electrical Engineering, vol. 475, pp. 149-155, 2018.[Abstract]


When the technology of VLSI circuits scales down to nanometer region, the parameter variation has a great impact on the circuit performance. Traditional false path filtering methods which use normal corner-based timing analysis miss some of the critical false paths or true paths. Viability analysis is one of the most accurate methods for false path filtering. Statistical timing analysis, which models the parameter variation statistically, becomes a promising variation-aware solution in the digital circuit design at the nanometer era. Thus, statistical viability analysis improves the accuracy in finding false paths or true paths in a design. For further optimization, the concept of gate sizing is used along with viability analysis. The criticality for gate selection is evaluated through viability analysis. The analysis and optimization are carried out on ISCAS 85 benchmark circuits. For a sample circuit C2670, a delay reduction of 10.99% is obtained with a slight increase in power of 0.65% and area overhead of 0.63%. © Springer Nature Singapore Pte Ltd. 2018.

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2016

Ramesh S. R. and Jayaparvathy, R., “Improved Statistical Static Timing Analysis Using Refactored Timing Graphs”, Journal of Computational and Theoretical Nanoscience, vol. 13, pp. 8879-8884, 2016.[Abstract]


Timing analysis is an important aspect in chip design which has the major attributes as speed and accuracy. Static Timing Analysis (STA) and Statistical Static Timing Analysis (SSTA) are the two existing timing engines to serve this task. The data handling in SSTA is a crucial task as it determines the speed or arrival time calculation. Circuits are converted as timing graphs and refactoring technique is applied to reduce the accuracy reduction caused by the replicated literals. We have developed a new methodology which uses refactoring technique with a view to speed up the computation. Parallel processing reduces the execution time. Certain nodes of the graph require serial processing. Hence an efficient data handling methodology was adopted on timing graphs. The proposed model was tested on ISCAS 85 benchmark and an increase in speed was obtained. A speed of 2×was achieved for parallel processing and this idea can be further used in criticality computation.

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2015

P. L. Paleri and Ramesh S. R., “Early Stage FPGA Architecture Development by Exploiting Dependence on Logic density”, International Journal Of Applied Engineering Research, vol. 10, no. 11, pp. 28889-28902, 2015.

2015

Ramesh S. R. and Jayaparvathy, R., “Probabilistic activity estimator and timing analysis for LUT based circuits”, International Journal of Applied Engineering Research, vol. 10, pp. 33238-33242, 2015.[Abstract]


Low power VLSI has received tremendous attention due to power constraints in designs. This paper details a survey on switching activity estimation techniques. It also presents a computationally efficient activity estimator which is probabilistic in nature. This estimator is faster and accurate. Simulation based approach is practically impossible for large circuits. More statistical parameters related to activity estimation are incorporated to improve the accuracy. This methodology is implemented on MCNC benchmarks. LUT mapping is done using the logic synthesis tool ABC. Spatial correlation is considered by computing the activities at each LUT. Power estimation using Synopsys Design Compiler tool gave 18% reduction in dynamic power for optimized circuits. Timing analysis plays an important role in circuit design. Statistical Timing Analysis (STA) is performed and the delay analysis is obtained. An effective tradeoff between timing and power were reported. © Research India Publications.

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2014

B. P. J and Ramesh S. R., “A Survey of SSTA Techniques with Focus on Accuracy and Speed”, International Journal of Computer Applications, vol. 89, no. 7, pp. 21-25, 2014.[Abstract]


Timing analysis plays a vital role in chip design, which analyze whether a chip design meets the timing constraints. The main objectives of timing analysis are speed and accuracy. There are two engines for timing analysis namely Statistical Timing Analysis (STA) and Statistical Static Timing Analysis (SSTA). VLSI CAD has been gaining a lot of interest in both STA and SSTA. As technology continues to advance deeper in to the nanometer regime, a tight control on the process parameters is increasingly difficult. To account these process parameters which are probabilistic in nature while performing timing analysis SSTA is preferred. The main goal of SSTA is to improve the accuracy without any reduction in speed by considering process variations. This paper presents a survey of SSTA approaches and techniques for improving accuracy and speed by considering the topological correlations and spatial correlations. More »»

2012

Ramesh S. R. and .P.J, A., “Toggle Rate Estimation Technique for 4-Input LUT based FPGA Circuits”, International Journal of Engineering Research and Applications , vol. 02, no. 3, pp. 198-203, 2012.[Abstract]


Power dissipation of a VLSI chip was not a concern in the past. A lot of effort has been put into synthesis for speed and area, power optimization has been explored only recently. Since power estimation is the foremost step in any low power design; this work concentrates on developing a technique that estimates the toggle rates for circuits implemented on a 4-input LUT based FPGA using probabilistic technique. The aim of this work is to develop a toggle rate estimation technique with improved accuracy by incorporating the effects of correlation of logic signals and glitches. This approach is tested on a set of MCNC circuits. The ABC logic synthesis system is used for LUT mapping.

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2012

A. P.V and Ramesh S. R., “An Approach towards Logic Synthesis by Functional Decomposition”, International Journal of Engineering Research and Applications , vol. 2, no. 3, pp. 324-330, 2012.[Abstract]


This paper surveys some of the basic principles behind logic synthesis. A few methods of logic synthesis are also discussed. Functional decomposition is an efficient technique for synthesis of logic circuits targeted on Look Up Table based FPGAs. It decomposes any circuit into a network of sub circuits. A method of functional decomposition for single output XOR based circuits is presented. It utilizes Gauss Jordan elimination, a method based on linearity, to decompose the circuits. The method was tested on a set of MCNC benchmark circuits in Blif format, and was successful in decomposing circuits efficiently. In case of XOR based circuits, the XOR relationship between the different sub circuits can be exposed by this method. A reduction in area was obtained due to this in case of large XOR based circuits and hence can be used for area driven logic synthesis. More »»

Publication Type: Conference Paper

Year of Publication Title

2017

Ramesh S. R. and Jayaparvathy, R., “Toggle Rate Estimation and Glitch Analysis on Logic Circuits”, in 2017 IEEE International Workshop On Integrated Power Packaging (IWIPP), 2017.[Abstract]


Toggle rate estimation is critical in the area of chip design, as it plays a major role in the power dissipation of a chip. This work presents a method to estimate the net toggle rate of a gate level circuit considering the effects of spatial correlation, temporal correlation and glitches and a comparison with LUT based methods is carried out. Previous works have addressed only on LUT based methods. The presence of glitches is accounted for using the timing analysis information, which is obtained using Statistical Static Timing Analysis. Accurate estimation of occurrence of glitches is crucial as it significantly increases the toggle rate. The toggle rate estimation technique using Statistical Static Timing Analysis was tested on gate level benchmark circuits and a comparison with LUT benchmarks were also carried out. The toggle rate estimated on gate level circuits show16% increase in accuracy when compared to LUT based benchmarks.

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2014

B. P. J and Ramesh S. R., “A comparison on timing analysis using probabilistic approaches”, in Communications and Signal Processing (ICCSP), 2014 International Conference on, 2014.[Abstract]


This paper presents a comparison on various timing analysis methods. Timing analysis is a critical step in any digital integrated circuits. Static timing analysis is a method to validate the timing performance of a digital circuit without requiring simulation. Technology and the process scaling to nanometer regime have lead to significant increase in process variations. These variations are needed to incorporate in static timing analysis. In the proposed method the delays of the gates and the arrival time are modeled by probabilistic distributions. The gate delays and the arrival time are modeled by using the operations statistical convolution integration and the statistical maximum. The delay values used is extracted from the standard delay format file for each gate. The method is tested by using various ISCAS benchmark circuits. Further statistical static timing analysis with arrival time at 3σ points away from the mean is calculated. The statistical static timing analysis results are found to be more accurate as it considers process variations. More »»

2012

Ramesh S. R. and P.V, A., “Area and speed aware Decomposition of Logic circuits for Look Up Table based FPGAs”, in Third International Conference on Intelligent Information Systems and Management(IISM), RVS College of Engineering and Technology, Coimbatore, 2012.

2010

M. .B and Ramesh S. R., “Online Noise Reduction Technique for Mobile Communication Using LABVIEW”, in International Conference on Embedded Systems (ICES) , by EEE Department, Coimbatore Institute of Technology, Coimbatore , 2010.

2010

S. .K and Ramesh S. R., “Design and Implementation of an Optimized Double Precision Floating Point Divider using Cache Memory”, in International Conference on Embedded Systems (ICES 2010) , EEE Department, Coimbatore Institute of Technology, Coimbatore, 2010.

2010

A. Baby, Raju, R., and Ramesh S. R., “Cross talk Effects on Mixed Signal CMOS ICs”, in International Conference on Advances in Information Communication Technology and VLSI Design , 2010.

Publication Type: Conference Proceedings

Year of Publication Title

2017

V. Vinod, Eswar, K., Vishnuvardhan, P., Srikanth, G., and Ramesh S. R., “VLSI Implementation of LNS Arithmetic Unit by LUT Partitioning”, 2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI). pp. 2241-2245, 2017.[Abstract]


The main motto of every electronic industry is to achieve low power. An efficient way to achieve this is by adapting different architectural modifications in the design. This paper proposes low power implementation of Logarithmic Number System (LNS) arithmetic unit on a FPGA. Power reduction is achieved by partitioning technique. The influence of partitioned memory on the power dissipated and delay required for performing arithmetic operations like add and sub in LNS are measured. Two design parameters namely MSB and LSB techniques are exploited to minimize the power dissipation. Only one of the sub-LUT is activated upon each operation which depends on MSB or LSB and also on the sign of operands. The synthesis is carried out using Xilinx ISE and the hardware is implemented on ZYBO Zynq-7000 development board. A considerable amount of reduction in power was obtained

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2014

Ramesh S. R., priya.V, S., Reddy, N. S., Mogi, V. M. Abitha, and .S.Sakthi, K., “An Efficient FIR Filter Design using CSE Method”, International Conference on Intelligent Engineering Systems . Department of ECE, Easa College of Engineering and Technology, Coimbatore., 2014.

2012

P. Ja Anju and Ramesh S. R., “Toggle rate estimation technique for FPGA circuits considering spatial correlation”, 2012 3rd International Conference on Computing, Communication and Networking Technologies, ICCCNT 2012. Coimbatore, Tamilnadu, 2012.[Abstract]


The interest in low power chips and systems are driven by both business and technical needs. Since power estimation is the foremost step in any low power design, this work concentrates on developing a technique that estimates the toggle rates for circuits implemented on a 4 input LUT based FPGA. Basically there are two methods of power estimation namely simulation based and probabilistic approach. Simulation based approach is more accurate that the later, but this method is computationally very expensive, practically impossible for large circuits. So, probabilistic method is a solution for this problem. They require only one time simulation and hence they are faster. This advantage is available at the cost of loss of accuracy. So this work focuses on improving the accuracy of probabilistic approach by incorporating more statistical parameters related to toggle rate estimation. This approach is tested on a set of MCNC circuits. The ABC logic synthesis system is used for LUT mapping. This method does a power modeling of FPGA circuits under spatial correlation by computing the transitions at each LUT by processing them in topological order. Gate Delays are also considered in this approach. © 2012 IEEE.

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2011

Ramesh S. R., Dr. Bala Tripura Sundari B., and .N, N., “Dataflow Transformation for Optimization of Digital/DSP Circuits”, Third National Conference on Recent Trends in Communication, Computation & Signal Processing organized by Department of ECE,Amrita School of Engineering, Ettimadai . 2011.

2010

Ramesh S. R., .S.M, L., and .T, A., “On-chip FPGA Implementation of OFDM Receiver Components”, First International Conference on Emerging Trends in Signal Processing and VLSI Design. Department of ECE, Guru Nanak Engineering College, Ibrahimpatnam, 2010.

2010

M. .B and Ramesh S. R., “Speech CODEC for Single Channel Applications Using LABVIEW”, Second National Conference on Recent Trends in Communication, Computation & Signal Processing(RTCSP2010). Department of ECE, Amrita School of Engineering , Ettimadai, 2010.

2010

Ramesh S. R. and .K, S., “Design of an Area Optimized Double Precision Floating Point Divider on FPGA”, International Conference on Intelligent Information Systems & Management-(IISM10). RVS College of Engineering and Technology, Coimbatore, 2010.

2010

Ramesh S. R., Scaria, A., and Nath.D, B., “A Systolic Architecture for Efficient Colour to Grey Scale Conversion and Reconstruction”, International Conference on Emerging Trends in Signal Processing and VLSI Design. Department of ECE, Guru Nanak Engineering College, Ibrahimpatnam., 2010.

2010

S. Manojna.D, .S, S. S., and Ramesh S. R., “VLSI Implementation of Asynchronous CDMA using Matched Filter”, International Conference on Communication and Computational Intelligence. 2010.

2009

R. .S and Ramesh S. R., “FPGA Implementation of a Low Density Parity Check Code Decoder using Min Sum Algorithm”, National Conference on Emerging trends in Communication Engineering. Department of ECE, Trichy Engineering College, Trichy, 2009.