Our Faculty

• 2020: Ph.D in VLSI Design (Static Timing Analysis)
  Anna University, Chennai
• 2007: M.E in VLSI Design
  Anna University, Chennai/ Arulmigu Kalasalingam College of Engineering
• 2005: B.E in ECE
  Anna University, Chennai/ Cape Institute of Technology

Undergraduate Courses Handled

• CMOS Integrated Circuits
• Electronics Engineering
• Electronic Circuits
• VLSI Design
• VLSI Technology
• VLSI System Design
• Digital Electronics
• Digital IC Design

Post-Graduate / Ph.D. Courses Handled

• Solid State Devices
• CMOS Digital Integrated Circuits
• Micro Electromechanical Systems
• Static Timing Analysis
• Analysis and Design of Mixed Signal VLSI Circuits
• VLSI Fabrication Technology
• Physical Design

Research Expertise

Ph. D scholars are working under him in domains such as Stochastic Computing, VLSI Testing, Design of Hardware Accelerators and Hardware Security. Currently, 4 PG students are carrying out research in the domain of Hardware Security under his supervision. One batch of UG students is working in QCA design.

Academic Research – PG Projects

PG Projects

• A Lightweight Ensemble Framework for Gate-Level Hardware Trojan Detection
• An Efficient Approach for Hardware Trojan Detection Based on Side-Channel Analysis
• Detection of Hardware Trojan Horse using Unsupervised Learning Approach
• Simulation Based Hardware Trojan Detection Using Path Delay Analysis
• FPGA Implementation of High Performance Precise Signed and Unsigned Multiplier using Ternary 6-LUT Architecture
• Test Vector Generation and Sensitivity Analysis for Hardware Trojan Detection in Compact Rare Nodes
• A MUX based Latch Technique for Hardware Trojan Detection
• Hardware Trojan Detection using Ring Oscillator
• Flip Flop Based Approach for Logic Encryption Techniques
• An Approach for Statistical Parameter Estimation and Test pattern Generation
• Power and Area Efficient Booth Multiplier
• MAC Unit design and its impact on a Trained Neural Network
• Hybrid Adder Design for High Speed Applications
• Power and Delay Efficient ALU using Vedic Techniques
• An Efficient Booth Multiplier using Probabilistic Approach
• An Efficient Linear Pipeline Circuit with Optimal Power Delay Product using Soft Edge Flip flops
• Analytical Modeling of Logic Resource Utilization for Early-Stage FPGA Architecture Development
• Statistical Static Timing Analysis Using Parallel Processing of Timing Graphs
• Design And Implementation of 1D Discrete Multiwavelet Transform for Infrasound Classification
• Statistical Timing Analysis Using Probabilistic Approaches
• Decomposition And Synthesis of XOR Based Logic Circuits For LUT Based FPGAs
• Probabilistic Activity Estimator For4-input LUT Based FPGA Circuits
• Data Flow Transformation for Optimization of Digital/DSP Circuits
• Design of an Optimized Double Precision Floating Point Divider Using Cache Memory and a Multiplier
• FPGA Implementation of Low-Density Parity Check Code Decoder

 UG Projects

• Design of RAM Structure using Quantum Dot Cellular Automata
• Compact Low- Power QCA based Parity Generator for Nanoscale Computing
• Implementation of Mirror Adder Using Multilayer Approach in QCA
• FPGA Implementation of Power and Area Efficient 32 bit MAC Unit
• A Signed Vedic Multiplier using Redundant Binary Representation
• Hardware Trojan Detection using Supervised Machine Learning
• Development of a System to measure Hemoglobin non-invasively
• Low Delay VLSI Architecture Design for Logarithmic Multiplication
• A Low Power Cubic Computation Unit using Vedic Techniques
• Design of Low power Binary Square rooter using Reversible Logic
• Design of Power Efficient Approximate Multipliers
• FPGA Implementation of Low power LNS Arithmetic Unit by LUT Partitioning
• A Comparative analysis on Static and Statistical Timing Techniques
• An Efficient FIR Filter Design Using Common Sub Expression Elimination Method
• Multimode Floating – Point Adder and Multiplier

Teaching

• VLSI Design
• VLSI Technology
• VLSI System Design
• Digital Electronics
• CMOS Digital Integrated Circuits
• Micro Electromechanical Systems
• Static Timing Analysis
• Analysis and Design of Mixed Signal VLSI Circuits
• VLSI Fabrication Technology
• Physical Design

• Received Best Paper Award for the paper titled “Rectifying the Impact of Multiple Cell Upsets in Memory Devices,” in the 2024 International Conference on Computer, Electronics, Electrical Engineering & their Applications (IC2E3-2024), organized by National Institute of Technology, Uttarakhand during 6th -7th June 2024.

Served as Journal Reviewer for:

• Alexandria Engineering Journal, Computers & Security, Engineering Applications of Artificial Intelligence, Expert Systems with Applications, Integration, Results in Engineering.

TPC Member for the following Conferences:

• 30th International Symposium on VLSI Design and Test (VDAT 2026), organized by Jaypee Institute of Information Technology, Noida during 20-22 August 2026.
• 29th International Symposium on VLSI Design and Test (VDAT 2025), organized by IIT Ropar, IIT Mandi during 7-9 August 2025
• 1st IEEE International Conference on Radio Frequency Communication and networks (RFCoN 2025), School of Electrical and Electronics Engineering, Sastra Deemed University, Thanjavur during 19-20 June 2025.
• 14th IEEE International Conference on Communication Systems and Network Technologies, VIT Bhopal during 7-9 March 2025.
• 10th IEEE International Conference on Wireless Communications Signal Processing and Networking (WiSPNET), SSN College of Engineering, 20-22 March 2025.
• 3rd International Conference on Computer, Electronics, Electrical Engineering and Their Applications (IC2E3-2025), NIT Uttarakhand, 15-16 May, 2025.
• 4th IEEE Bangalore Humanitarian Technology Conference, B-HTC 2025, KLS’s Gogte Institute of Technology, Belagavi, North Karnataka, 25-26 April, 2025.
• 2024 IEEE North Karnataka Subsection Flagship International Conference (NKCon) Basaveshwar Engineering College, Bagalkote, from 21 -22 September, 2024.