Publications

Abstract : We present the design of an ultra-low phase noise, low power 28GHz integer-N (N=32) frequency synthesizer for 5G applications. The proposed design consists of a self-biased PMOS core LC VCO which shows ultra-low phase noise with lowest power consumption and high output power. To achieve frequency division in K-band, a CML frequency divider (CMLD) (divide-by-2) is used, and an Injection locked frequency divider (ILFD) (divide-by-2) is used for low power frequency division in Ku-band. The design is realized using UMC 65 nm CMOS technology, and shows a phase noise of -129.72 dBc/Hz @ 1 MHz offset from the oscillation frequency 27.84 GHz when the input reference signal frequency is 870 MHz, consuming a total power of 39.74 mW from 1.2V supply voltage. The PLL operating frequency range is 26.5 GHz to 29.5 GHz. The Figure of merit (FOM) of entire PLL is -202 dBc/Hz, and the figure of merit with tuning FOMT is -215 dBc/Hz.