Back close

Analysis of low power open core protocol bridge interface using VHDL

Publication Type : Conference Paper

Publisher : Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE

Source : Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE, IEEE, Trivandrum, p.357-362 (2011)

Url : https://ieeexplore.ieee.org/document/6069334

Campus : Coimbatore

School : School of Engineering

Department : Computer Science

Year : 2011

Abstract : System on Chip (SoC) design is becoming challenging due to its complexity and the necessity of Intellectual Properties (IP) reuse to shorten the design time. An efficient bus protocol for the core communication between IP block is OCP. Open Core Protocol (OCP) defines the only non-proprietary, openly licensed, core centric protocol with high-performance, bus-independent interface between IP cores that reduces design time, design risk, and manufacturing costs and promote IP core reusability for SOC designs. Bus Bridge interconnects other bus standard to OCP. I2C is a simple bi-directional two wire bus for efficient inter IC control. This paper focus on the design and implementation of Bus Bridge using OCP master and I2C slave protocol. The power reduction using Multi voltage design is the important feature of the paper. The developed FSM's for OCP and I2C were implemented in VHDL and the Synthesis is done using Xilinx ISE 10.1 and Synopsys ASIC synthesis tool design compiler.

Cite this Research Publication : Dr. Ramesh Bhakthavatchalu, Deepthy, G. R., Vidhya, S., and Nisha, V., “Analysis of low power open core protocol bridge interface using VHDL”, in Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE, Trivandrum, 2011, pp. 357-362.

Admissions Apply Now