Publication

Abstract : Digital computers perform variety of information tasks. Among the functions encountered are the various arithmetic operations. The most important arithmetic operation is the addition of binary digits. A complementing adder is a combinational circuit that performs the arithmetic operations of addition and subtraction with binary numbers depending on the control input is designed. The reversible logic, the most emerging technology is used to develop the adder and extended to the transistor level by single electron transistor for nanoprocessors, one of the low power nano devices. DKGP reversible gate can be modeled as a full adder and full subractor. Connecting 8 full adders in cascade produces a binary adder for two 8-bit numbers. The subtraction circuit is included by providing a complementing circuit to the 8-bit adder circuit constitute complementing adder. The circuit is simulated using ORCAD and the results are proven that the complementing adder using SET dissipate highly considerable low power related to the CMOS.