Publication Type : Other
Source : 2003
Url : http://www.google.co.in/patents/US6569747
Campus : Amritapuri
School : Centre for Cybersecurity Systems and Networks, School of Engineering
Center : TBI
Department : cyber Security, Chemical
Year : 2003
Abstract : Shallow trench isolation techniques are disclosed in which a nitride layer is formed on a semiconductor substrate, and a trench is formed through the nitride layer and into the semiconductor substrate. The nitride layer is removed prior to filling the isolation trench, and the fill material is planarized using a fixed-abrasive CMP process to mitigate or avoid step height in the shallow trench isolation process.
Cite this Research Publication : K. Achuthan and Sahota, K., “Methods for trench isolation with reduced step height”. 2003.