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Publication Type : Conference Paper
Publisher : Proceedings of the 2017 International Conference on Wireless Communications, Signal Processing and Networking, WiSPNET 2017
Source : Proceedings of the 2017 International Conference on Wireless Communications, Signal Processing and Networking, WiSPNET 2017, Institute of Electrical and Electronics Engineers Inc., Volume 2018-January, p.650-653 (2018)
ISBN : 9781509044412
Keywords : Charge pump, Charge pump circuits, Circuit oscillations, Current mismatch, Differential amplifiers, Divider, Locks (fasteners), Loop filter, Oscillistors, Phase comparators, Phase frequency detectors, Phase locked loops, Signal processing, Variable frequency oscillators, Voltage dividers, Wireless telecommunication systems
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2018
Abstract : The design of an Integer-N charge pump phase locked loop is presented in this paper, with emphasis on the current mismatch within the charge pump. The usage of differential amplifier in between the two limbs of the charge pump is found to reduce the current mismatch. The conventional charge pump requires 9 transistors and the proposed design reduces the current mismatch by 14%, with the inclusion of additional 3 transistors. The application intended for the PLL is 2.4 GHz, and the lock time obtained is 55 ns. The complete PLL circuit is implemented in 180 nm technology, with the NAND based PFD, and current starved type VCO based on 3-stage ring oscillator. The circuit consumes 13.32 mW of power, at the supply voltage of 1.8 V. © 2017 IEEE.
Cite this Research Publication : Aravinda K and Dr. T. K. Ramesh, “Integer-N charge pump phase locked loop with reduced current mismatch”, in Proceedings of the 2017 International Conference on Wireless Communications, Signal Processing and Networking, WiSPNET 2017, 2018, vol. 2018-January, pp. 650-653.